A 7-bit 1-GSa/s Cryo-CMOS ADC for Spin-Qubit Readout

Abstract

Quantum computing offers exponential speed-up for problems that are computationally intractable with classical computing. However, quantum processors with thousands to millions of quantum bits (qubits) are needed. Room-temperature electronics are used to control and readout today's qubits operating at cryogenic temperature. As the number of wires that can be placed between room temperature and the cryogenic chamber is limited, this creates a bottleneck in the scaling of quantum computers. Cryogenic CMOS (cryo-CMOS) electronics has been proposed to overcome this bottleneck. Operating the control electronics at cryogenic temperature, very close to the qubit, and controlling and reading out the qubits by frequency multiplexing relaxes the interconnect bottleneck. This work tackles this challenge by focusing on the qubit readout system and more specifically on the spin-qubit readout. The main target is to develop a cryo-CMOS analog-to-digital converter (ADC) for such an application. 
The readout of frequency multiplexed spin-qubits using RF reflectometry is considered the target application. The non-idealities of the RF-reflectometry scheme are simulated and analyzed for the qubit multiplexing and included in the system-level modeling of the readout chain. The target design specifications of the ADC are derived from such system-level simulations, resulting in the need for a 1 GSa/s ADC with ENOB > 6 bits operating at 4 K for the readout ~20 frequency-multiplexed spin-qubits with a BER of 1e-03.
Based on those specifications, this work proposes a 2-channel time-interleaved ADC using a Loop-Unrolled Successive Approximation Register (LU-SAR) ADC. The loop unrolling technique in combination with time-interleaving achieves the sampling rate of 1.1 GSa/s. The design includes the integration of a dynamic amplifier as an input driver and the generation of all required timing for the ADC core and the dynamic amplifier. Foreground calibration of the SAR comparator offset is included to achieve the linearity specifications. The ADC has been designed in TSMC 40nm CMOS technology and taped out for fabrication. After  calibration of comparator offset and calibration of the delay/gain mismatch between the two time-interleaved channels, the simulated performance of the ADC demonstrates an ENOB of 6.35 bits, SNDR of 40 dB, SFDR >50 dBc. The Figure-of-Merit of the designed ADC is 25.2 fJ/conv at 1 GSa/s sampling rate (including the driving amplifier and the clocking circuitry), which is significantly higher than the prior cryogenic ADCs and on-par with room-temperature state-of-the-art ADCs. The proposed ADC contributes towards the realization of future large-scale quantum computers, comprising million-qubit quantum processors integrated with cryogenic CMOS interface electronics.