A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8 #x2013;19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS

Conference paper (2016)

Authors

C.C. Li Taiwan Semiconductor Manufacturing Company (TSMC)

T.H. Tsai Taiwan Semiconductor Manufacturing Company (TSMC)

M Chen Taiwan Semiconductor Manufacturing Company (TSMC)

A. Ronchini Ximenes (OLD)Applied Quantum Architectures

R.B. Staszewski University College Dublin, Electronics -

Min Shueh Yuan Taiwan Semiconductor Manufacturing Company (TSMC)

Chia Chun Liao Taiwan Semiconductor Manufacturing Company (TSMC)

C.H. Chang Taiwan Semiconductor Manufacturing Company (TSMC)

T.C. Huang Taiwan Semiconductor Manufacturing Company (TSMC)

H.Y. Liao Taiwan Semiconductor Manufacturing Company (TSMC)

C.T. Lu Taiwan Semiconductor Manufacturing Company (TSMC)

H.Y. Kuo Taiwan Semiconductor Manufacturing Company (TSMC)

K. Hsieh Taiwan Semiconductor Manufacturing Company (TSMC)

Research Group

(OLD)Applied Quantum Architectures

Tuning Jitter CMOS integrated circuits Q-factor DCO Transformers Clocks Phase locked loops Capacitors MOSFET circuits Digital phase locked loops FinFETs FinFET CMOS LC-tank-based ADPLL Capacitor banks Fractional-N all-digital PLL Frequency 10.8 GHz to 19.3 GHz Frequency reference clock Inverter-based ring-oscillator PLL Magnetic coupling transformer Metastability-resolution scheme Size 10 nm Time 725 fs

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http://resolver.tudelft.nl/uuid:ff9b6d10-8999-4b57-822b-eacd7930a751

Published Date

22-09-2016

Language

English

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Research Group

(OLD)Applied Quantum Architectures

Abstract

A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.