A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine
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A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.@en
