A 10-bit Digital to Time Converter with a Phase Noise Filter

Master thesis (2023)

Authors

T. Wang Electrical Engineering, Mathematics and Computer Science

Contributors

S. Du Electronic Instrumentation - EEMCS (supervisor 1)
S.M. Alavi Electronics - EEMCS (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2023 Tianyu Wang
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Published Date

31-08-2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

The growing demand for asynchronous data communication leads to a growing demand for CDR systems to recover the sampling clock of the received data. The DTC in the CDR system is the main jitter source of the recovered data. A low-jitter DTC is required to generate data of low-jitter performance, calling for the application of a phase noise filter. Currently, most phase noise filters are based on the charge injection technique, which can only filter the phase noise of the DLL-based DTC.

This thesis presents a new phase noise filter, which can filter both the DLL and PI phase noise. The proposed phase noise filter is inspired by the noise transfer function from the phase detector’s input to the delay locked loop(DLL) output of a type-II DLL, which shows a first-order low-pass transfer function. The noise suppression pole frequency is adjustable and can be modified by changing the
gain of each component in the circuit. In addition, by carefully placing the frequency of the LDO’s pole, second-order noise filtering can be realized.

During design, a 10-bit DTC is constructed first and the proposed filter is placed behind the DTC to verify the effectiveness of the filter. The design achieves the post-layout level. The simulation results show that the DTC’s phase noise drops from 1.099 psrms to 315.9 fsrms with the filter. The area is 695 μm × 693.5 μm. The design consumes 42.3 mW with 1.8V supply in 180nm BCD technology.