High-speed asynchronous digital interfaces

High-speed asynchronous digital interfaces: Exploiting the spatiotemporal correlations of event-based sensor data

Zhan, Fengwei (TU Delft Electrical Engineering, Mathematics and Computer Science; TU Delft Microelectronics)

Frenkel, C.P. (mentor)
Makinwa, K.A.A. (graduation committee)
Gao, C. (graduation committee)
Chauvaux, N. (graduation committee)

Delft University of Technology

Electrical Engineering | Microelectronics

2023-08-28

With the introduction of event-based cameras, such as the dynamic vision sensor (DVS), new opportunities have arisen for low-latency real-time visual data processing. Unlike traditional frame-based cameras that capture entire frames at fixed intervals, each pixel in an event-based camera operates asynchronously, generating an event whenever its brightness change exceeds a certain threshold. Although DVS sensors inherently surpass traditional frame-based cameras in capturing transient, high-speed phenomena, their performance bottleneck is usually located in their address event representation (AER) readout interfaces. The commonly used row-scanning synchronous AER, which encodes events in a full row at once, offers high throughput. However, this approach also introduces inherent delays that limit its use in applications requiring high temporal resolution. Conversely, while AER schemes based on asynchronous digital circuits surpass synchronous schemes in temporal resolution, their event-by-event transmission approach limits their overall throughput.

This work proposes a novel high-speed asynchronous AER interface, leveraging spatiotemporal correlations in DVS event-based data, to optimize the tradeoff between temporal resolution and throughput. Supported by the recently proposed open-source asynchronous design toolkit (ACT) flow for asynchronous digital circuits, we propose an address fuser to be integrated into the hierarchical token ring (HTR) AER scheme. This address fuser creates a spatiotemporal window to exploit the inherent spatiotemporal correlations in DVS data. After verification at both switch- and transistor-level simulations, we benchmarked our design against the conventional HTR AER scheme using a representative set of input scenarios. Our design achieved 196% of the throughput for multi-event transmissions when all pixels were activated simultaneously, at the expense of an acceptable 18% latency increase for single-event transmissions with a 10-ns temporal window.

Asynchronous digital circuits
Event-based vision
Address event representation

http://resolver.tudelft.nl/uuid:a9c930e5-1bc7-472a-bbbf-56ce26b4b8b8

2024-08-25

Student theses

master thesis

© 2023 Fengwei Zhan