Low-Offset Band-Pass Signal Shaper with High Time Resolution in 40 nm CMOS Technology

Conference paper (2023)

Authors

A.R. Mohammad Zaki Electronic Instrumentation - EEMCS
S. Nihtianova Electronic Instrumentation - EEMCS
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Copyright: © 2023 A.R. Mohammad Zaki, S. Nihtianova
DOI: https://doi.org/10.1109/IECON51785.2023.10312049
Low-offset Power-efficient High time resolution Readout integrated circuit ROIC Charge-sensitive amplifier Analog frontend Signal shaper block Lownoise
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Published Date

2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

State-of-the-art readout integrated circuits (ROICs) operating in particle-counting mode are gravitating toward high time resolution, low-noise, and low-power analog readout frontends to detect and register the arrival time of charge signals with a high accuracy. To achieve a time resolution of a few nanoseconds, an intermediate stage, known as a signal shaper block, is the preferred solution in the readout frontend, as it compensates for the inter-symbol interference-induced errors by realizing a band-pass transfer function. This paper presents the design methodology and experimental characterization of a state-of-the-art, high time resolution, low-offset, and power-efficient band-pass signal shaper block intended for fitting the voltage signals generated by a charge-sensitive amplifier (CSA) as a function of charge signals as small as 160 aC, into timeframes of 2.5 ns with 17 times offset attenuation while consuming 0.17 mW of power. Detailed information about the operation principle of this CSA, designed in TSMC 40 nm MS/RF CMOS technology, is reported in a previous publication.