A 10Gb/s Cryogenic Clock and Data Recovery System with Low Jitter

A 10Gb/s Cryogenic Clock and Data Recovery System with Low Jitter

de Jong, Lennart (TU Delft Electrical Engineering, Mathematics and Computer Science)

Babaie, M. (mentor)
Spirito, M. (graduation committee)
Muratore, D.G. (graduation committee)

Delft University of Technology

2021-10-19

A key issue in current quantum computing interfaces is the dense interconnect between electronics at cryogenic temperature (CT) and room temperature (RT). Recently, progress has been made to move more control electronics from RT to CT, reducing interconnect overhead. The next step towards minimal interconnect is a direct wireline interface between RT and CT. This work presents a full­rate 10 Gb/s clock­and­data recovery circuit for a high speed serial link receiver operating at CT.

A novel phase detector is utilized to reduce power consumption by removing the need for both a pulse generator at the input and, a buffer between the phase detector and voltage controlled oscillator. Additionally, a digital delay­locked loop is added to improve the retiming margin, achieving higher jitter tolerance. Implemented in 40­nm CMOS, post­layout simulation shows a core power consumption of 3.89 mW from a 1.1­V supply at 10 Gb/s, producing an rms­jitter of 84 fs and an estimated jitter tolerance
of 1.1 UIpp at 10 MHz.

Clock and Data Recovery
Low Jitter
Cryo-CMOS
CDR

http://resolver.tudelft.nl/uuid:d3e2296a-89e9-4422-8f37-4b24c6dc3d07

2023-10-19

Student theses

master thesis

© 2021 Lennart de Jong