Thermal Analysis of Cu Pillars

Master thesis (2021)

Authors

D.X. Desouza Electrical Engineering, Mathematics and Computer Science

Contributors

Kouchi Zhang Electronic Components, Technology and Materials - EEMCS (mentor)
H.W. van Zeijl Electronic Components, Technology and Materials - EEMCS (mentor)
René van den Berg NXP Semiconductors (mentor)
Nick Thomassen NXP Semiconductors (mentor)
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright: © 2021 Denver Desouza
More Info
expand_more

Published Date

30-06-2021

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

THERMAL management is a very crucial step to ensure the reliability of Integrated Circuits (IC)s. The increase in power density has resulted in the formation of multiple, high-intensity, and non-uniform hotspots. This has not only affected the lifetime but also the performance of several devices. Optimization of the package design and layout are the methods investigated to solve this problem. In flip-chip packaging, each IC product varies with respect to power densities, die area, pin-count, laminate and PCB layers, etc. It is therefore important in understanding how the arrangement and geometry of each layer (in particular the interconnect layer) impacts the overall thermal management.