Print Email Facebook Twitter A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW Title A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW Author Bolatkale, M. (NXP Semiconductors) Breems, LJ (TU Delft Electronic Instrumentation) Rutten, Robert (NXP Semiconductors) Makinwa, K.A.A. (TU Delft Electronic Instrumentation) Date 2011 Abstract A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter. Subject Analog-to-digital conversionbase stationsCMOS analog integrated circuitscontinuous-time filterscontinuous-time sigma-delta modulationdelta-sigma modulatormulti-bitoversampling ADCsradio receiverswireless communication To reference this document use: http://resolver.tudelft.nl/uuid:13d808df-b4f5-4c6b-8781-15eecde87911 DOI https://doi.org/10.1109/JSSC.2011.2164963 ISSN 0018-9200 Source IEEE Journal of Solid State Circuits, 46 (12), 2857-2868 Bibliographical note Accepted Author Manuscript Part of collection Institutional Repository Document type journal article Rights © 2011 M. Bolatkale, LJ Breems, Robert Rutten, K.A.A. Makinwa Files PDF 2095722a_06029947.pdf 2.09 MB Close viewer /islandora/object/uuid:13d808df-b4f5-4c6b-8781-15eecde87911/datastream/OBJ/view