Print Email Facebook Twitter Defect and Fault Modeling Framework for STT-MRAM Testing Title Defect and Fault Modeling Framework for STT-MRAM Testing Author Wu, L. (TU Delft Computer Engineering; CognitiveIC) Rao, Siddharth (IMEC) Taouil, M. (TU Delft Computer Engineering; CognitiveIC) Cardoso Medeiros, G. (TU Delft Computer Engineering; CognitiveIC) Fieback, M. (TU Delft Computer Engineering; CognitiveIC) Marinissen, Erik Jan (IMEC) Kar, Gouri Sankar (IMEC) Hamdioui, S. (TU Delft Quantum & Computer Engineering; CognitiveIC) Department Quantum & Computer Engineering Date 2019-12-17 Abstract STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This article presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed. Subject fault modelsmanufacturing defectsSTT-MRAMtest development To reference this document use: http://resolver.tudelft.nl/uuid:61d606bb-abfc-465d-959e-2f5ca6fbf713 DOI https://doi.org/10.1109/TETC.2019.2960375 ISSN 2168-6750 Source IEEE Transactions on Emerging Topics in Computing, 9 (2), 707-723 Part of collection Institutional Repository Document type journal article Rights © 2019 L. Wu, Siddharth Rao, M. Taouil, G. Cardoso Medeiros, M. Fieback, Erik Jan Marinissen, Gouri Sankar Kar, S. Hamdioui Files PDF 08935208.pdf 4.19 MB Close viewer /islandora/object/uuid:61d606bb-abfc-465d-959e-2f5ca6fbf713/datastream/OBJ/view