Hard-to-Detect Fault Analysis in FinFET SRAMs

Cardoso Medeiros, G.; Fieback, M.; Wu, L.; Taouil, M.; Bolzani Poehls, L. M.; Hamdioui, S.

doi:10.1109/TVLSI.2021.3071940

Hard-to-Detect Fault Analysis in FinFET SRAMs

Title

Hard-to-Detect Fault Analysis in FinFET SRAMs

Author

Cardoso Medeiros, G. (TU Delft Computer Engineering)
Fieback, M. (TU Delft Computer Engineering)
Wu, L. (TU Delft Computer Engineering)
Taouil, M. (TU Delft Computer Engineering)
Bolzani Poehls, L. M. (Pontifical Catholic University of Rio Grande do Sul; Rheinisch-Westfälische Technische Hochschule)
Hamdioui, S. (TU Delft Quantum & Computer Engineering)

Department

Quantum & Computer Engineering

Date

2021

Abstract

Manufacturing defects can cause hard-to-detect (HTD) faults in fin field-effect transistor (FinFET) static random access memories (SRAMs). Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field failures. This article presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage during manufacturing testing. We first define the fault space for SRAMs and classify all faults in the space. Following this, we perform a systematic fault analysis based on injecting resistive defects in a memory cell, inspecting its behavior, and identifying HTD faults. Furthermore, we survey existing test solutions and discuss their HTD fault coverage and limitations. Based on our analysis, it is clear that no single test solution can fully detect all HTD faults, thus leading to test escapes. Hence, there is a need for new and more efficient test solutions. Improved detection of HTD faults could be achieved by using parametric test solutions, proposing solutions that cover yet-untargeted HTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions. These new approaches would reduce test escapes and therefore improve the quality of FinFET SRAMs.

Subject

Fault analysis
fin field-effect transistor (FinFET)
hard-to-detect (HTD) faults
static random access memory (SRAM)
test solutions
testing

To reference this document use:

http://resolver.tudelft.nl/uuid:9172918d-8358-49a9-b4b6-799a7a8db9ca

DOI

https://doi.org/10.1109/TVLSI.2021.3071940

ISSN

1557-9999

Source

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29 (6), 1271-1284

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