Print Email Facebook Twitter Performance Analysis and Cost-Performance Tradeoffs of a High Performance Partially Buffered Crossbar Switch Title Performance Analysis and Cost-Performance Tradeoffs of a High Performance Partially Buffered Crossbar Switch Author Skalis, N. Contributor Bertels, K. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Computer Engineering Programme Embedded Systems Date 2010-07-01 Abstract Why is it hard to build high-speed routers? Because high-speed routers are like marriages; they are unpredictable, provide no guar- antees, and become vulnerable in adversity. High-speed networks including the Internet backbone suffer from a well-known problem; packets arrive on high-speed routers much faster than commodity memory can support. On a 10 Gb/s link, packets can arrive ev- ery 32 ns, while memory can only be accessed once every 50 ns. If we are unable to bridge this performance gap, then (1) We can- not create Internet routers that reliably support links >10 Gb/s. (2) Routers cannot support the needs of real-time applications such as voice, video conferencing, multimedia, gaming, etc., that require guaranteed performance. Network operators expect certain perfor- mance characteristics; for example, if the arrival rate is less than the router’s advertised capacity, they can reasonably assume the router can handle the traffic. Somewhat surprisingly, no commercial router can do this today! The emphasis is put on the switching architecture of a router. This thesis lays down a theoretical foundation for the Partially Buffered Crossbar switches and is about managing and resolving the prefer- ences and contention for memory between packets from participating inputs and outputs in a switch. By combining the theory of fluid models, Lyapunov functions and the pigeonhole principle, the requirements for devising practical algorithms which can provide guarantees and emulate the performance of the ideal Output Queued switch and approximate the optimal Maximum Weight Matching scheduler are drawn up. The solutions described in this thesis, relax the memory access and band- width constraint, in fact, there is no better switching architecture described till now in terms of memory requirements and practicality regarding its achieved performance. Moreover, this thesis derives the first study of scheduling unicast and multicast traffic simultaneously in a Partially Buffered Crossbar switch. Subject switchrouterscheduling To reference this document use: http://resolver.tudelft.nl/uuid:b0590baf-4af3-49f7-9a69-4718842bfc0f Part of collection Student theses Document type master thesis Rights (c) 2010 Skalis, N. Files PDF Nikos_Skalis.pdf 1008.42 KB Close viewer /islandora/object/uuid:b0590baf-4af3-49f7-9a69-4718842bfc0f/datastream/OBJ/view