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Improving the usability and scalability of FINN, a DNN compiler for FPGAs
Improving the usability and scalability of FINN, a DNN compiler for FPGAs
Integration of a convolutional neural network for speech-to-text recognition in an FPGA compiler flow
Integration of a convolutional neural network for speech-to-text recognition in an FPGA compiler flow
Exploring the Limits of Query Pushdown for SQL Acceleration on FPGAs
Exploring the Limits of Query Pushdown for SQL Acceleration on FPGAs
Near-Realtime Low Power Epileptic Seizure Detection Using ANNs
Near-Realtime Low Power Epileptic Seizure Detection Using ANNs
Implementation and Evaluation of Packed-SIMD Instructions for a RISC-V Processor
Implementation and Evaluation of Packed-SIMD Instructions for a RISC-V Processor
FPGAs in Big Data
FPGAs in Big Data: On the transparent and efficient acceleration of big data frameworks
Exploring Feasibility of FPGAs in Implantable Medical Devices
Exploring Feasibility of FPGAs in Implantable Medical Devices
FPGA Based Deep Learning Accelerator for RF Applications
FPGA Based Deep Learning Accelerator for RF Applications: A Design Framework
Dynamic cache configuration for the ρ-VEX platform
Dynamic cache configuration for the ρ-VEX platform
Real-time airborne signal processing for Synthetic Aperture Radar
Real-time airborne signal processing for Synthetic Aperture Radar
Ultra low latency deep neural network inference for gravitational waves interferometer
Ultra low latency deep neural network inference for gravitational waves interferometer: *
High Throughput Parallel Computation with High Bandwidth Memory on FPGA
High Throughput Parallel Computation with High Bandwidth Memory on FPGA
Design for a TCP/IP transparent FPGA-based network diode
Design for a TCP/IP transparent FPGA-based network diode: To what extent is it possible to implement a network diode on an FPGA under realistic network environments, using the Transmission Control Protocol?
Towards Real-Time Olivary Neuron Modeling
Towards Real-Time Olivary Neuron Modeling
Dataflow Hardware Design for Big Data Acceleration Using Typed Interfaces
Dataflow Hardware Design for Big Data Acceleration Using Typed Interfaces
Transparently Accelerating Spark SQL Code on Computing Hardware
Transparently Accelerating Spark SQL Code on Computing Hardware
Scaling up data analytics in Python using multiple FPGAs
Scaling up data analytics in Python using multiple FPGAs
An Elliptic Curve Cryptography Acceleration Core for OpenVPN on an FPGA Softcore
An Elliptic Curve Cryptography Acceleration Core for OpenVPN on an FPGA Softcore
Optimizing Memory Mapping for Dataflow Inference Accelerators
Optimizing Memory Mapping for Dataflow Inference Accelerators: Efficient Memory Utilization on FPGAs
Solving convex optimization problems on FPGA using OpenCL
Solving convex optimization problems on FPGA using OpenCL
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