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Li, Shenyang (author)This thesis describes the design of a 3rd order 1-bit delta-sigma modulator whose input-signal range (0 to 1.95V) exceeds its supply voltage (1.2V). By using a passive input stage and a single-OTA resonator, this beyond-the-rails modulator realizes a 3rd order loop filter with only two amplifiers instead of the usual three and thus achieves...master thesis 2023
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Li, Haoyuan (author)This thesis discusses the basic architecture, design details, circuit implementation, and measurements of a digital class D current driver.<br/>The driver contains two main parts: a digital control loop and analog circuits.<br/>Parts of the important part in the digital control loop contain noise shaper, plant compensator, and cable capacitance...master thesis 2021