29.2 A Cryo-CMOS Controller with Class-DE Driver and DC Magnetic-Field Tuning for Color-Center-Based Quantum Computers

29.3 A Cryo-CMOS Receiver with 15K Noise Temperature Achieving 9.8dB SNR in 10μs Integration Time for Spin Qubit Readout

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

A Cryo-CMOS PLL for Quantum Computing Applications

Cryogenic-Aware Forward Body Biasing in Bulk CMOS

A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing

19.1 A 300MHz-BW, 27-to-38dBm In-Band OIP3 sub-7GHz Receiver for 5G Local Area Base Station Applications

A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion

A Cryo-CMOS DAC-based 40 Gb/s PAM4 Wireline Transmitter for Quantum Computing Applications

CMOS integrated circuits for the quantum information sciences

Impedance Standard Substrate Characterization and em model definition for Cryogenic and Quantum-Computing Applications

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

A Benchmark of Cryo-CMOS 40-nm Embedded SRAM/DRAMs for Quantum Computing

A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing

A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications

A Four-Way Series Doherty Digital Polar Transmitter at mm-Wave Frequencies

Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs

A Low-Jitter and Low-Spur Charge-Sampling PLL

A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV _ppSupply Ripple

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications