Advances in Magnetics Roadmap on Spin-Wave Computing

Magnonics addresses the physical properties of spin waves and utilizes them for data processing. Scalability down to atomic dimensions, operation in the GHz-to-THz frequency range, utilization of nonlinear and nonreciprocal phenomena, and compatibility with CMOS are just a few of many advantages offered by magnons. Although magnonics is still...

Rapid Design-Space Exploration for Low-Power Manycores under Process Variation utilizing Machine Learning

Design-space exploration for low-power manycore design is a daunting and time-consuming task which requires some complex tools and frameworks to achieve. In the presence of process variation, the problem becomes even more challenging, especially the time associated with trial-and-error selection of the proper options in the tools to obtain the...

Demeter: A Fast and Energy-Efficient Food Profiler Using Hyperdimensional Computing in Memory

Food profiling is an essential step in any food monitoring system needed to prevent health risks and potential frauds in the food industry. Significant improvements in sequencing technologies are pushing food profiling to become the main computational bottleneck. State-of-the-art profilers are unfortunately too costly for food profiling. Our...

Using STLs for Effective In-field Test of GPUs

Editor's notes: GPUs have seen an increased adoption in autonomous systems. This article assesses the fault coverage that can be attained through software self-test strategies for in-field test of GPUs. - Nicola Nicolici, McMaster University

Energy-efficient In-Memory Address Calculation

Computation-in-Memory (CIM) is an emerging computing paradigm to address memory bottleneck challenges in computer architecture. A CIM unit cannot fully replace a general-purpose processor. Still, it significantly reduces the amount of data transfer between a traditional memory unit and the processor by enriching the transferred information....

KrakenOnMem: A Memristor-Augmented HW/SW Framework for Taxonomic Profiling

State-of-the-art taxonomic profilers that comprise the first step in larger-context metagenomic studies have proven to be computationally intensive, i.e., while accurate, they come at the cost of high latency and energy consumption. Table Lookup operation is a primary bottleneck of today's profilers. In this paper, we first propose TL-PIM, a...

Review of Manufacturing Process Defects and Their Effects on Memristive Devices

Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective...

Modeling Static Noise Margin for FinFET based SRAM PUFs

In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM)) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated...

System-level sub-20 nm planar and FinFET CMOS delay modelling for supply and threshold voltage scaling under process variation

Standard low power design utilizes a variety of approaches for supply and threshold control to reduce dynamic and idle power. At a very early stage of the design cycle, the V_dd and V_th values are estimated, based on the power budget, and then used to scale the delay and estimate the design performance. Furthermore,...

Time-division Multiplexing Automata Processor

Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into...

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V _dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power...

Memristive devices for computation-in-memory

CMOS technology and its continuous scaling have made electronics and computers accessible and affordable for almost everyone on the globe; in addition, they have enabled the solutions of a wide range of societal problems and applications. Today, however, both the technology and the computer architectures are facing severe challenges/walls making...

RRAM Variability and its Mitigation Schemes

Emerging technologies such as RRAMs are attracting significant attention, due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures (such as process variation due to their nano-scale structure) have...