CMOS-Compatible PureGaB Ge-on-Si APD pixel arrays

Pure gallium and pure boron (PureGaB) Ge-on-Si photodiodes were fabricated in a CMOS compatible process and operated in linear and avalanche mode. Three different pixel geometries with very different area-to-perimeter ratios were investigated in linear arrays of 300 pixels with each a size of 26 × 26 μm2. The processing of anode contacts at the...

Insights to emitter saturation current densities of boron implanted samples based on defects simulations

Emitter saturation current densities, Joe have been investigated with different boron implantation dose and annealing conditions. The higher thermal budgets used here are shown experimentally to improve Joe, implying more complete defect dissolution. Simulations show that significant degradation in Joe can be attributed to the presence of...

Arsenic-doped high-resistivity-silicon epitaxial layers for integrating low-capacitance diodes

An arsenic doping technique for depositing up to 40-?m-thick high-resistivity layers is presented for fabricating diodes with low RC constants that can be integrated in closely-packed configurations. The doping of the as-grown epi-layers is controlled down to 5 × 1011 cm?3, a value that is solely limited by the cleanness of the epitaxial reactor...

Chemical Vapor Deposition of ?-Boron Layers on Silicon for Controlled Nanometer-Deep p+n Junction Formation

Nanometer-thick amorphous boron (?-B) layers were formed on (100) Si during exposure to diborane (B2H6) in a chemical vapor deposition (CVD) system, either at atmospheric or reduced pressures, at temperatures down to 500°C. The dependence of the growth mechanism on processing parameters was investigated by analytical techniques, such as...

Improved RF Devices for Future Adaptive Wireless Systems Using Two-Sided Contacting and A1N Cooling

This paper reviews special RF/microwave silicon device implementations in a process that allows two-sided contacting of the devices: the back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the...

On the Mechanisms Governing Aluminum-Mediated Solid-Phase Epitaxy of Silicon

Mechanisms governing the aluminum-mediated solid-phase epitaxy of Si on patterned crystalline Si substrates have been identified by studying the deposited material as a function of growth conditions when varying parameters such as temperature, growth time, and layer-stack properties. Early growth stages can be discerned as first formation of ...

Accurate SIMS Doping Profiling of Aluminum-Doped Solid-Phase Epitaxy Silicon Islands

A procedure has been implemented for a quantitative aluminum-doping profiling of µm-scale aluminum-induced solid-phase-epitaxy (SPE) Si islands formed at 400°C. The aluminum concentration was measured to be 1–2×1019 cm?3, which is about 10 times higher than previously reported electrical activation levels. The elemental concentration was...