Interaction graph-based characterization of quantum benchmarks for improving quantum circuit mapping techniques

To execute quantum circuits on a quantum processor, they must be modified to meet the physical constraints of the quantum device. This process, called quantum circuit mapping, results in a gate/circuit depth overhead that depends on both the circuit properties and the hardware constraints, being the limited qubit connectivity a crucial...

Code extraction from Agda to HVM

Dependently typed languages such as Agda have the potential to revolutionize the way we write software because they allow the programmer to catch more bugs at compile time than classical languages. Nonetheless, dependently typed languages are hardly used in practice. One of the reasons is the lack of mature compilers for them.<br/>This paper...

Lasagne: a static binary translator for weak memory model architectures

The emergence of new architectures create a recurring challenge to ensure that existing programs still work on them. Manually porting legacy code is often impractical. Static binary translation (SBT) is a process where a program's binary is automatically translated from one architecture to another, while preserving their original semantics....

Time-sensitive intermittent computing meets legacy software

Tiny energy harvesting sensors that operate intermittently, without batteries, have become an increasingly appealing way to gather data in hard to reach places at low cost. Frequent power failures make forward progress, data preservation and consistency, and timely operation challenging. Unfortunately, state-of-the-art systems ask the...

LLVM-based ?-VEX compiler

This thesis describes the development of an LLVM-based compiler for the ?-VEX processor. The ?-VEX processor is a runtime re- configurable VLIW processor. Currently, two compilers exist that target the ?-VEX processor: a HP-VEX compiler and a GCC-based compiler. We show that both compilers have disadvantages that are very dif- ficult to fix....

Quantitative analysis and visualization of memory access patterns