A Highly Linear Temperature Sensor Operating up to 600°C in a 4H-SiC CMOS Technology

In this work, a highly linear temperature sensor based on a silicon carbide (SiC) p-n diode is presented. Under a constant current biasing, the diode has an excellent linear response to the temperature (from room temperature to 600°C). The best linearity (coefficient of determination ${R}^{{2}}$ = 99.98%) is achieved when the current density...

A linearity improvement method for CIS column-parallel SAR ADC using two-step conversion

This paper presents a new 2-step SAR ADC architecture for image sensors in machine vision applications. This structure effectively improves the structural problems of the image sensor caused by the area occupied by the ADC, such as linearity and temporal noise performance. In this work, we designed a two-step SAR ADC using a 6-bit SAR ADC and...

A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications

By introducing three different techniques, this article, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next,...

The Zoom ADC: An Evolving Architecture

Zoom ADCs combine a coarse SAR ADC with a fine delta-sigma modulator (?SM) to efficiently obtain high energy efficiency and high dynamic range. This makes them well suited for use in various instrumentation and audio applications. However, zoom ADCs also have drawbacks. The use of over-ranging in their fine modulators may limit SNDR, large...

A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA...

Load-Modulation-Based IMD3 Cancellation for Millimeter-Wave Class-B CMOS Power Amplifiers Achieving EVM < 1.2%

This letter presents a novel load-modulation-based 3rd-order intermodulation distortion (IMD3) cancellation technique for class-B CMOS power amplifiers (PAs). In a class-B PA, the IMD3 generated by the 3rd-order transconductance ( $g_{m3}$ ) and the gain compression have opposite signs, and thus, they can cancel each other at specific bias...

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order &amp;#x0394;&amp;#x03A3; time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still...

A 280 μW Dynamic Zoom ADC With 120 dB DR 118 dB SNDR in 1 kHz BW

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (&amp;lt;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential &amp;#x0394; &amp;#x03A3; ADC. Compared to previous zoom ADCs,...

A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW

Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (&lt;1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and...

Structured electronic design of high-pass ΣΔ converters and their application to cardiac signal acquisition

Achieving an accurate sub-Hz high-pass (HP) cutoff frequency and simultaneously a high accuracy of the transfer function is a challenge in the implementation of analog-to-digital converters for biomedical ExG signals. A structured electronic design approach based on state-space forms is proposed to develop HPΣΔ modulators targeting high accuracy...

Video Acceleration Magnification

The ability to amplify or reduce subtle image changes over time is useful in contexts such as video editing, medical video analysis, product quality control and sports. In these contexts there is often large motion present which severely distorts current video amplification methods that magnify change linearly. In this work we propose a method...