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Wu, L. (author)In recent years, wireless personal area network (WPAN) applications have triggered the needs for low-cost and low-power PLLs which also provide good performance. All-digital phased-locked loops (ADPLLs) are preferred over their analog counterparts in nanoscale CMOS technology due to their flexibility, configurability, small area and easy...master thesis 2014
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Chen, P. (author)The technology scaling favors the Digital PLLs, which is reconfigurable. In the traditional fractional-N ADPLL, whether counter-based or divider based, DCO and TDC are the main two power consuming blocks. Modifying the phase detection part based on phase prediction makes the architecture more energy-efficient. The new architecture leads to the...master thesis 2014
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Chillara, V.K. (author)RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios. Compared to analog PLLs, all-digital phase-locked loops (ADPLLs) are preferred in nanoscale CMOS, as they offer benefits of smaller area, programmability, capability of extensive self...master thesis 2013
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Drago, Salvatore (author), Leenaerts, Domine M.W. (author), Nauta, Bram (author), Sebastiano, F. (author), Makinwa, K.A.A. (author), Breems, LJ (author)<br/><br/>journal article 2010