Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼ 100 M H z in...

Highly-conformal sputtered through-silicon vias with sharp superconducting transition

This paper describes the microfabrication and electrical characterization of aluminum-coated superconducting through-silicon vias (TSVs) with sharp superconducting transition above 1 K. The sharp superconducting transition was achieved by means of fully conformal and void-free DC-sputtering of the TSVs with Al, and is here demonstrated in up...

Superconducting High-Aspect Ratio Through-Silicon Vias with DC-Sputtered Al for Quantum 3D integration

This paper presents the fabrication and electrical characterization of superconducting high-aspect ratio through-silicon vias DC-sputtered with aluminum. Fully conformal and void-free coating of 300 μm-deep and 50 μmwide vias with Al, a CMOS-compatible and widely available superconductor, was made possible by tailoring a funneled sidewall...

Fabrication of Al-based superconducting high-aspect ratio TSVs for quantum 3D integration

We describe a microfabrication process that, thanks to a specifically tailored sidewall profile, enables for the first-time wafer-scale arrays of high-aspect ratio through-silicon vias (TSVs) coated with DC-sputtered Aluminum, achieving at once superconducting and CMOS-compatible 3D interconnects. Void-free conformal coating of up to 500μm...

Vacuum assisted liquified metal (VALM) TSV filling method with superconductive material

A novel, simple, low-cost method for the void-free filling of high aspect ratio (HAR) through-silicon-vias (TSVs) is presented. For the first-time pure indium, a type-I superconductor metal, is used to fill HAR vias, 300 to 500 μm in depth and 50 to 100 μm in diameter. The low electrical resistivity achieved without sintering, its...

Wafer Level Packaging With Nano Metal Paste Interconnects For UV-C LEDs

: Light emitting diodes (LEDs) have made remarkable progress since their invention and today they can be found in a wide range of applications such as TV remotes, automotive headlamps, general lighting, traffic signals, camera flashes, display and screens. LEDs that emit light in the ultraviolet-C (UV-C) range are used in applications such as...

High-performance, Cost-effective 3D Stacked Wide-Operand Adders

Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology introduces new design opportunities for wide operand width addition units. Different from state of the art direct folding proposals we introduce two cost-effective 3D Stacked Hybrid Adders with identical tier structure, which potentially makes the manufacturing of hardware wide...

Thermal-Aware Design and Runtime Management of 3D Stacked Multiprocessors

The sustained increase in computational performance demanded by next-generation applications drives the increasing core counts of modern multiprocessor systems. However, in the dark silicon era, the performance levels and integration density of such systems is limited by thermal constraints of their physical package. These constraints are more...

Super-growth of CNTs based on ZrN for TSV application

This thesis has explored the possibility of using carbon nanotubes (CNT) as a novel material for through-silicon vias (TSV) in 3D-integrated circuits. With the steady downscaling trend of the semiconductor industry, a major limiting factor to the overall performance of the device is the delay from interconnects; a trend that is worsening over...

Modeling and Extraction of Through-Silicon Vias

3D is entering the world of Integrated Circuits. While interconnects have always been three-dimensional, the actual silicon inside an IC was essentially still planar. The introduction of the Through-Silicon Via changes that, by allowing connections to be made from one side of a die through its silicon substrate to the other side of the die, so...

A DfT architecture for 3D-SICs based on a standardizable die wrapper

Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular...

Test impact on the overall die-to-wafer 3D stacked IC cost

One of the key challenges in 3D Stacked-ICs (3D-SIC) is to guarantee high product quality at minimal cost. Quality is mostly determined by the applied tests and cost trade-offs. Testing 3D-SICs is very challenging due to several additional test moments for the mid-bond stacks, i.e., partially created stacks. The key question that this paper...