This thesis describes the design and simulation of a capacitively-coupled autozeroed and chopped operational amplifier in the TSMC high-voltage BCD 0.18 μm 5 V technology. It uses chopping and autozeroing to achieve high precision (10 μV offset and 50 nV/√Hz noise density) and a capacitively-coupled input stage to safely handle beyond-the-rails 50 V input voltages. The amplifier employs a pseudo-continuous time architecture that periodically autozeroes a single signal path, which is also chopped. Compared to amplifiers with ripple-reduction loops, this approach should potentially result in area and power savings. However, it also means that the signal path is periodically broken during a short deadtime, during which the signal path is autozeroed. Since the presence of the deadtime comes with a noise penalty, the amplifier’s clocking scheme has been optimized to reduce the length of the deadtime relative to the length of the two amplification phases. The simulated performance of the resulting amplifier is comparable with that of other precision amplifiers, while its chip area should be lower, resulting in lower production costs.