AS
A.W.G. Spierings
info
Please Note
<p>This page displays the records of the person named above and is not linked to a unique person identifier. This record may need to be merged to a profile.</p>
1 records found
1
Digital Interface Design for a Sub-Sea Data Acquisition System
Design and Verification of a High-Speed SPI Interface with Reclocking Architecture for a Subsea DAQ System
Bachelor thesis
(2026)
-
R. Ali, A.W.G. Spierings, K.A.A. Makinwa, Arthur Admiraal, F.J.P. van Mourik, T.D. Onstein
A digital interface was designed and verified for a subsea data acquisition system operating at pressures of up to 500 bar. The interface connects an FPGA outside the pressure vessel to converter electronics inside the vessel through a 16-wire bulkhead connector.
Serial communication protocols were implemented in VHDL for both a DAC and an ADC operating at 2 MSps. The wire-count constraint drove the selection of serial interfaces and the placement of a low-jitter clock source on the converter PCB to meet the 100 dB SNR system requirement.
Hardware verification confirmed correct operation across the full output range. The system was pressure-tested at 500 bar, with no measurable degradation in performance.
...
Serial communication protocols were implemented in VHDL for both a DAC and an ADC operating at 2 MSps. The wire-count constraint drove the selection of serial interfaces and the placement of a low-jitter clock source on the converter PCB to meet the 100 dB SNR system requirement.
Hardware verification confirmed correct operation across the full output range. The system was pressure-tested at 500 bar, with no measurable degradation in performance.
...
A digital interface was designed and verified for a subsea data acquisition system operating at pressures of up to 500 bar. The interface connects an FPGA outside the pressure vessel to converter electronics inside the vessel through a 16-wire bulkhead connector.
Serial communication protocols were implemented in VHDL for both a DAC and an ADC operating at 2 MSps. The wire-count constraint drove the selection of serial interfaces and the placement of a low-jitter clock source on the converter PCB to meet the 100 dB SNR system requirement.
Hardware verification confirmed correct operation across the full output range. The system was pressure-tested at 500 bar, with no measurable degradation in performance.
Serial communication protocols were implemented in VHDL for both a DAC and an ADC operating at 2 MSps. The wire-count constraint drove the selection of serial interfaces and the placement of a low-jitter clock source on the converter PCB to meet the 100 dB SNR system requirement.
Hardware verification confirmed correct operation across the full output range. The system was pressure-tested at 500 bar, with no measurable degradation in performance.