24 records found
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Evaluation methodology for data communication-aware application partitioning
Quipu: a statistical model for predicting hardware resources
Extensions of the hArtes tool chain
Quantitative hardware prediction modeling for hardware/software co-design
The Q² profiling framework: driving application mapping for heterogeneous reconfigurable platforms
Profile-guided application partitioning for heterogeneous reconfigurable platforms
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler
The hArtes tool chain
Communication-aware HW/SW co-design for heterogeneous multicore platforms
High Level Quantitative Hardware Prediction Modeling using Statistical methods
Advanced Profiling of Applications for Heterogeneous Multi-Core Platforms
QUAD - a memory access pattern analyser
QUAD-quantitative usage analysis of data
Algorithms for the automatic extension of an instruction-set
A multipurpose clustering algorithm for task partitioning in multicore reconfigurable systems
High level quantitative interconnect estimation for early design space exploration
Automatic instruction-set extensionswith the linear complexity spiral search
A self-adaptive on-line task placement algorithm for partially reconfigurable systems
HaRTES toolchain early evaluation: profiling, compilation and HDL generation
Quantitative prediction for early design space exploration in Delft workbench: an outlook
