Jv
J. van der Kleij
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1
This thesis aims to evaluate the viability of using a Field Programmable Gate Array (FPGA) in a neural Implantable Medical Device (IMD). The primary motivation for incorporating FPGAs is their potential to support future functionalities, such as running neural networks for medical condition analysis but also advanced cybersecurity algorithms. These algorithms are compute-intensive, and accelerators like FPGAs offer advantages in terms of speed and efficiency. To assess the effectiveness of such a device, state-of-the-art Microcontroller Units (MCUs) commonly used in similar applications are employed as a reference. Comparisons are made between MCU-only platforms and hybrid platforms integrating both an MCU and an FPGA. Feasibility analysis considers operational modes and use cases based on various realistic scenarios. The results show mixed outcomes across scenarios. Under a 100% duty cycle, the FPGA demonstrates higher efficiency, consuming less active power than the MCU. However, at lower duty cycles, MCUs are generally more effective on average. The use of an FPGA becomes practical when power-gating techniques are applied to minimize power consumption during inactive periods.
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This thesis aims to evaluate the viability of using a Field Programmable Gate Array (FPGA) in a neural Implantable Medical Device (IMD). The primary motivation for incorporating FPGAs is their potential to support future functionalities, such as running neural networks for medical condition analysis but also advanced cybersecurity algorithms. These algorithms are compute-intensive, and accelerators like FPGAs offer advantages in terms of speed and efficiency. To assess the effectiveness of such a device, state-of-the-art Microcontroller Units (MCUs) commonly used in similar applications are employed as a reference. Comparisons are made between MCU-only platforms and hybrid platforms integrating both an MCU and an FPGA. Feasibility analysis considers operational modes and use cases based on various realistic scenarios. The results show mixed outcomes across scenarios. Under a 100% duty cycle, the FPGA demonstrates higher efficiency, consuming less active power than the MCU. However, at lower duty cycles, MCUs are generally more effective on average. The use of an FPGA becomes practical when power-gating techniques are applied to minimize power consumption during inactive periods.
Semi Bistatic Radar
Subgroup - Receiver Antenna
In this thesis, a design of a passive radar for use on a drone used in inhospitable areas where air traffic control is not available due to circumstances. The thesis focusses on the receiver chain and angle of arrival algorithm.
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In this thesis, a design of a passive radar for use on a drone used in inhospitable areas where air traffic control is not available due to circumstances. The thesis focusses on the receiver chain and angle of arrival algorithm.