Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer‐defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity‐BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard‐etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfab-rication compatible tools and methods. The use of the cavity‐BOX as a buried hard‐etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 μm‐thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity‐BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity‐BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

Accurate alignment between the cavities in cavity-SOI (c-SOI) wafers and lithography on the wafer surface is essential to advanced MEMS production. Existing alignment methods are well defined, but often require specialized equipment or costly software packages available only in professional manufacturing environments. It would be beneficial for the microfabrication world to be able to utilize standard alignment techniques and tools that are easily available also in smaller MEMS fabrication units and especially the majority of research facilities. Therefore, we demonstrate a feasible method for c-SOI wafer alignment using an ASML PAS5500/100 wafer stepper with standard software configuration by relocating ASML alignment markers towards wafer's edges and utilizing a terracing process to reveal them for alignment. Moreover, we characterize the magnitude and behavior of image offset errors that are introduced using this method. The offset error is found to be inversely proportional to the value of the coordinate in each axis, resulting in images being shifted towards the center of the wafer. The measured offset errors are <160 nm, and are suitable for most applications. To further minimize these errors we propose a simple model or database of the offsets. We conclude that this alternative alignment method is feasible for a number of MEMS applications, and could promote increased integration of c-SOI technology into advanced MEMS production.