Cavity‐box soi
Advanced silicon substrate with pre‐patterned box for monolithic mems fabrication
M.M. Kluba (TU Delft - EKL Processing)
J. Li (TU Delft - Electronic Components, Technology and Materials)
Katja Parkkinen (Research and Development, Technology, Okmetic Oy, Vantaa)
Marcus Louwerse (Philips Research)
Jaap Snijder (Philips Research)
R. Dekker (Philips Research, TU Delft - Electronic Components, Technology and Materials)
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Abstract
Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer‐defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity‐BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard‐etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfab-rication compatible tools and methods. The use of the cavity‐BOX as a buried hard‐etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 μm‐thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity‐BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity‐BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.
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