To be able to cope with the demands of next generation radar applications, a bandwidth of 400MHz is required. The SAR assisted CT ∆Σ ADC provides an energy efficient ADC, but needs improvements to cope with the bandwidth enlargement. This thesis examines the front end components and thus initially focuses on resolving the issues in the front end. Although bandwidth enlargement is possible, the APF limits the performance resulting in an inefficient two-stage architecture. For optimal system efficiency, the APF requirements must be relaxed, which is achieved by decreasing the amount of resolved bits in the coarse ADC. Due to this reduction in bits, more stages must be incorporated into the architecture. To facilitate this, power and error budgets are devised to visualize the effects of adding stages. Hereafter, the 2 bit coarse ADC is compared to a 3 bit coarse ADC. This results in a trade-off between the applicable gain (APF complexity) and the noise requirements of the front end. The five-stage (2-2-2-2-6 bit) architecture proves to be the most promising design to achieve the desired FoMs of 172dB. Finally, in an attempt to optimize power efficiency, the APF and LPF filter are revised. The open loop filter implementation is compared to a closed loop filter implementation. It shows that the open loop implementation exhibits very good power efficiency, but lacks in its linearity. The closed loop implementation achieves the requirements, but consumes a lot of power. To optimize power consumption, the first and second stage must be implemented with the closed loop filters, but the third and fourth stage must be implemented with the open loop filters.