Biomedical engineering focuses in advancing health care by taking advantage of the technological improvement. An important part of biomedical engineering is biomedical sensing, that focuses in the acquisition of biopotential signals. Through time, a lot of research has been done on the acquisition of biopotential signals and a variety of methods has been presented. The main goal of the front-end circuits of the biomedical sensing devices is to convert the analog value obtained by a sensor to its digital equivalent. In order to achieve an accurate conversion, the analog-to-digital converters used, need to achieve a medium resolution and a sampling frequency at the kilohertz range. Another important aspect in biomedical sensing devices is to achieve minimum power and area consumption. The properties of the biopotential signals and the requirements set by the biomedical applications, make the design of ADCs based on classical mixed architectures increasingly difficult, as technology scaling deteriorates the performance of the analog part of the devices. In the presented thesis, time-domain signal processing techniques have been used in order to develop a programmable resolution, low-voltage, low-power and small-area time-mode ADC for biomedical applications. The proposed time-mode ADC is a novel architecture and it is composed of a voltagecontrolled ring oscillator based analog-to-time converter, followed by an asynchronous, unfolded SAR, coarse TDC and an asynchronous, enhanced range. fine flash TDC, As the input is sensed, the analog-to-time converter, embeds the analog informationwithin the time period between a rising and a falling edge of the output signal. Following, the output time pulse is fed to the TDC that quantizes the pulse and produces the digital equivalent representation of the sensed value. The resolution of the ADC can be programmed from 8 to 10 bits. The delay elements of the coarse TDC are based on a novel modified version of Dynamic Leakage Suppresion delay elements. Moreover, a novel background calibration mechanism is introduced to correct the errors due to process variation. The calibration removes the offset and gain error of the ADC and achieves DNL and INL reduction. The integrated circuit has been implemented in a 65nm TSMC process and its performance has been evaluated through Cadence and Synopsys tools. The ADC uses a 0.5V supply voltage and consumes 771 nW for 10-bit resolution. The total area of the ADC is 0.01342 mm2. The maximum sampling rate is 2.2 KS/s. The DNL and INL of the 10 bit converter are +0.86/-0.83 and +0.88/-1.79 respectively. The simulation results indicate an SNDR of 61.3 dB and an ENOB of 9.8 bit for a 10mV peak-to-peak 1kHz input frequency.