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O.C. Akgün
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10 records found
1
On the longevity and inherent hermeticity of silicon-ICs
Evaluation of bare-die and PDMS-coated ICs after accelerated aging and implantation studies
Journal article
(2025)
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Kambiz Nanbakhsh, Ahmad Shah Idil, Callum Lamont, Csaba Dücső, Ömer Can Akgun, Domonkos Horváth, Kinga Tóth, Wouter Serdijn, Vasiliki Giagka, More authors...
Silicon integrated circuits (ICs) are central to the next-generation miniature active neural implants, whether packaged in soft polymers for flexible bioelectronics or implanted as bare die for neural probes. These emerging applications bring the IC closer to the corrosive body environment, raising reliability concerns, particularly for chronic use. Here, we evaluate the inherent hermeticity of bare die ICs, and examine the potential of polydimethylsiloxane (PDMS), a moisture-permeable elastomer, as a standalone encapsulation material. For this aim, the electrical and material performance of ICs sourced from two foundries was evaluated through one-year accelerated in vitro and in vivo studies. ICs featured custom-designed test structures and were partially PDMS coated, creating two regions on each chip, uncoated “bare die” and “PDMS-coated”. During the accelerated in vitro study, ICs were electrically biased and periodically monitored. Results revealed stable electrical performance, indicating the unaffected operation of ICs even when directly exposed to physiological fluids. Despite this, material analysis revealed IC degradation in the bare regions. PDMS-coated regions, however, revealed limited degradation, making PDMS a suitable IC encapsulant for years-long implantation. Based on the new insights, guidelines are proposed that may enhance the longevity of implantable ICs, broadening their applications in the biomedical field.
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Silicon integrated circuits (ICs) are central to the next-generation miniature active neural implants, whether packaged in soft polymers for flexible bioelectronics or implanted as bare die for neural probes. These emerging applications bring the IC closer to the corrosive body environment, raising reliability concerns, particularly for chronic use. Here, we evaluate the inherent hermeticity of bare die ICs, and examine the potential of polydimethylsiloxane (PDMS), a moisture-permeable elastomer, as a standalone encapsulation material. For this aim, the electrical and material performance of ICs sourced from two foundries was evaluated through one-year accelerated in vitro and in vivo studies. ICs featured custom-designed test structures and were partially PDMS coated, creating two regions on each chip, uncoated “bare die” and “PDMS-coated”. During the accelerated in vitro study, ICs were electrically biased and periodically monitored. Results revealed stable electrical performance, indicating the unaffected operation of ICs even when directly exposed to physiological fluids. Despite this, material analysis revealed IC degradation in the bare regions. PDMS-coated regions, however, revealed limited degradation, making PDMS a suitable IC encapsulant for years-long implantation. Based on the new insights, guidelines are proposed that may enhance the longevity of implantable ICs, broadening their applications in the biomedical field.
Dynamic Digital Twin
Diagnosis, Treatment, Prediction, and Prevention of Disease During the Life Course
Journal article
(2022)
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Skander Tahar Mulder, Amir-Houshang Omidvari, Anja J. Rueten-Budde, Rihan Hai, Can Akgün, David M.J. Tax, M.J.T. Reinders, Marcel Reinders, Valentijn Visch, More authors...
A digital twin (DT), originally defined as a virtual representation of a physical asset, system, or process, is a new concept in health care. A DT in health care is not a single technology but a domain-adapted multimodal modeling approach incorporating the acquisition, management, analysis, prediction, and interpretation of data, aiming to improve medical decision-making. However, there are many challenges and barriers that must be overcome before a DT can be used in health care. In this viewpoint paper, we build on the current literature, address these challenges, and describe a dynamic DT in health care for optimizing individual patient health care journeys, specifically for women at risk for cardiovascular complications in the preconception and pregnancy periods and across the life course. We describe how we can commit multiple domains to developing this DT. With our cross-domain definition of the DT, we aim to define future goals, trade-offs, and methods that will guide the development of the dynamic DT and implementation strategies in health care.
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A digital twin (DT), originally defined as a virtual representation of a physical asset, system, or process, is a new concept in health care. A DT in health care is not a single technology but a domain-adapted multimodal modeling approach incorporating the acquisition, management, analysis, prediction, and interpretation of data, aiming to improve medical decision-making. However, there are many challenges and barriers that must be overcome before a DT can be used in health care. In this viewpoint paper, we build on the current literature, address these challenges, and describe a dynamic DT in health care for optimizing individual patient health care journeys, specifically for women at risk for cardiovascular complications in the preconception and pregnancy periods and across the life course. We describe how we can commit multiple domains to developing this DT. With our cross-domain definition of the DT, we aim to define future goals, trade-offs, and methods that will guide the development of the dynamic DT and implementation strategies in health care.
In this paper, we present the design of a low-voltage, low-power, and small-area time-mode ADC (TM-ADC) for bio-signal sensing applications. The proposed time-mode ADC (TM-ADC) consists of a programmable oversampling ratio (OSR), voltage-controlled ring oscillator (VCRO) based analog-to-time converter (ATC), followed by an asynchronous unfolded SAR coarse TDC and an asynchronous, enhanced-range fine flash TDC. The integrated circuit has been implemented in a standard CMOS 65 nm process and its performance has been evaluated through extracted transient noise simulations. The ADC consumes 771 nW at a sampling rate of 2.2 kHz from a 0.5V supply voltage and achieves 10-bit resolution in a total area of 0.014 mm2. The simulation results indicate DNL and INL values of +0.86/-0.83 and +0.88/-1.79, respectively, an SNDR of 60.7 dB and an ENOB of 9.8 bits for a 10mV peak-to-peak signal 1kHz input signal.
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In this paper, we present the design of a low-voltage, low-power, and small-area time-mode ADC (TM-ADC) for bio-signal sensing applications. The proposed time-mode ADC (TM-ADC) consists of a programmable oversampling ratio (OSR), voltage-controlled ring oscillator (VCRO) based analog-to-time converter (ATC), followed by an asynchronous unfolded SAR coarse TDC and an asynchronous, enhanced-range fine flash TDC. The integrated circuit has been implemented in a standard CMOS 65 nm process and its performance has been evaluated through extracted transient noise simulations. The ADC consumes 771 nW at a sampling rate of 2.2 kHz from a 0.5V supply voltage and achieves 10-bit resolution in a total area of 0.014 mm2. The simulation results indicate DNL and INL values of +0.86/-0.83 and +0.88/-1.79, respectively, an SNDR of 60.7 dB and an ENOB of 9.8 bits for a 10mV peak-to-peak signal 1kHz input signal.
For mm-sized implants incorporating silicon integrated circuits, ensuring lifetime operation of the chip within the corrosive environment of the body still remains a critical challenge. For the chip's packaging, various polymeric and thin ceramic coatings have been reported, demonstrating high biocompatibility and barrier properties. Yet, for the evaluation of the packaging and lifetime prediction, the conventional helium leak test method can no longer be applied due to the mm-size of such implants. Alternatively, accelerated soak studies are typically used instead. For such studies, early detection of moisture/ion ingress using an in-situ platform may result in a better prediction of lifetime functionality. In this work, we have developed such a platform on a CMOS chip. Ingress of moisture/ions would result in changes in the resistance of the interlayer dielectrics (ILD) used within the chip and can be tracked using the proposed system, which consists of a sensing array and an on-chip measurement engine. The measurement system uses a novel charge/discharge based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18 μm 6-metal CMOS process. The platform was validated through a series of dry and wet measurements. The system can measure the ILD resistance with values of up to 0.504 peta-ohms, with controllable measurement steps that can be as low as 0.8 MΩ. The system works with a supply voltage of 1.8 V, and consumes 4.78 mA. Wet measurements in saline demonstrated the sensitivity of the platform in detecting moisture/ion ingress. Such a platform could be used both in accelerated soak studies and during the implant's life-time for monitoring the integrity of the chip's packaging.
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For mm-sized implants incorporating silicon integrated circuits, ensuring lifetime operation of the chip within the corrosive environment of the body still remains a critical challenge. For the chip's packaging, various polymeric and thin ceramic coatings have been reported, demonstrating high biocompatibility and barrier properties. Yet, for the evaluation of the packaging and lifetime prediction, the conventional helium leak test method can no longer be applied due to the mm-size of such implants. Alternatively, accelerated soak studies are typically used instead. For such studies, early detection of moisture/ion ingress using an in-situ platform may result in a better prediction of lifetime functionality. In this work, we have developed such a platform on a CMOS chip. Ingress of moisture/ions would result in changes in the resistance of the interlayer dielectrics (ILD) used within the chip and can be tracked using the proposed system, which consists of a sensing array and an on-chip measurement engine. The measurement system uses a novel charge/discharge based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18 μm 6-metal CMOS process. The platform was validated through a series of dry and wet measurements. The system can measure the ILD resistance with values of up to 0.504 peta-ohms, with controllable measurement steps that can be as low as 0.8 MΩ. The system works with a supply voltage of 1.8 V, and consumes 4.78 mA. Wet measurements in saline demonstrated the sensitivity of the platform in detecting moisture/ion ingress. Such a platform could be used both in accelerated soak studies and during the implant's life-time for monitoring the integrity of the chip's packaging.
This paper presents the design of an ultra-low energy neural network that uses time-mode signal processing). Handwritten digit classification using a single-layer artificial neural network (ANN) with a Softmin-based activation function is described as an implementation example. To realize time-mode operation, the presented design makes use of monostable multivibrator-based multiplying analogue-to-time converters, fixed-width pulse generators and basic digital gates. The time-mode digit classification ANN was designed in a standard CMOS 0.18 μm IC process and operates from a supply voltage of 0.6 V. The system operates on the MNIST database of handwritten digits with quantized neuron weights and has a classification accuracy of 88%, which is typical for single-layer ANNs, while dissipating 65.74 pJ per classification with a speed of 2.37 k classifications per second. This article is part of the theme issue 'Harmonizing energy-autonomous computing and intelligence'.
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This paper presents the design of an ultra-low energy neural network that uses time-mode signal processing). Handwritten digit classification using a single-layer artificial neural network (ANN) with a Softmin-based activation function is described as an implementation example. To realize time-mode operation, the presented design makes use of monostable multivibrator-based multiplying analogue-to-time converters, fixed-width pulse generators and basic digital gates. The time-mode digit classification ANN was designed in a standard CMOS 0.18 μm IC process and operates from a supply voltage of 0.6 V. The system operates on the MNIST database of handwritten digits with quantized neuron weights and has a classification accuracy of 88%, which is typical for single-layer ANNs, while dissipating 65.74 pJ per classification with a speed of 2.37 k classifications per second. This article is part of the theme issue 'Harmonizing energy-autonomous computing and intelligence'.
One key obstacle in employing silicon integrated circuits in flexible implants is ensuring a long-term operation of the chip within the wet corrosive environment of the body. For this reason, throughout the years, various biocompatible insulating materials have been proposed, yet, evaluating their long-term encapsulation performance on representative silicon samples still remains to be the main challenge. For this aim, in this work, a sensitive platform is introduced that can track the integrity of the chip against water and ion ingress. This platform is developed to be used for long-term monitoring of chip integrity and study of encapsulation layers in wet environments. The platform comprises a sensing array and a measurement engine and operates by tracking the changes in the inter-layer dielectric resistance within the chip. The proposed system uses a novel charge/discharge-based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18 µm 6-metal CMOS process. For chip validation, dry and wet measurements in saline are presented in this paper.
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One key obstacle in employing silicon integrated circuits in flexible implants is ensuring a long-term operation of the chip within the wet corrosive environment of the body. For this reason, throughout the years, various biocompatible insulating materials have been proposed, yet, evaluating their long-term encapsulation performance on representative silicon samples still remains to be the main challenge. For this aim, in this work, a sensitive platform is introduced that can track the integrity of the chip against water and ion ingress. This platform is developed to be used for long-term monitoring of chip integrity and study of encapsulation layers in wet environments. The platform comprises a sensing array and a measurement engine and operates by tracking the changes in the inter-layer dielectric resistance within the chip. The proposed system uses a novel charge/discharge-based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18 µm 6-metal CMOS process. For chip validation, dry and wet measurements in saline are presented in this paper.
This paper presents the design of an extremely low-energy biosensing platform that utilizes voltage to time conversion and time-mode signal processing to sense and accommodate electrophysiological biosignals that will be later sent remotely using a simple and low power communication scheme. The electrode input is fed to a chain of monostable multivibrators used as analog-to-time converters, which create time pulses whose widths are proportional to the input signal. These pulses are transmitted to an external receiver by means of single-pulse harmonic modulation as the communication scheme, at a carrier frequency of 10 MHz. The platform is designed to be implemented in a standard 0.18μm IC process with an energy dissipation per sample per channel of 42.72 pJ, including communication, operating from a supply voltage of 0.6V with an input referred noise of 12.3 μVrms. The resulting SNR for OSR=256 is 35.19 dB, and the system’s power consumption at a sampling and communication rate of 256 Hz is 10.94 nW.
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This paper presents the design of an extremely low-energy biosensing platform that utilizes voltage to time conversion and time-mode signal processing to sense and accommodate electrophysiological biosignals that will be later sent remotely using a simple and low power communication scheme. The electrode input is fed to a chain of monostable multivibrators used as analog-to-time converters, which create time pulses whose widths are proportional to the input signal. These pulses are transmitted to an external receiver by means of single-pulse harmonic modulation as the communication scheme, at a carrier frequency of 10 MHz. The platform is designed to be implemented in a standard 0.18μm IC process with an energy dissipation per sample per channel of 42.72 pJ, including communication, operating from a supply voltage of 0.6V with an input referred noise of 12.3 μVrms. The resulting SNR for OSR=256 is 35.19 dB, and the system’s power consumption at a sampling and communication rate of 256 Hz is 10.94 nW.
With the continuous developments in science and engineering, specifically in the fields of electronics and manufacturing, implantable electronic devices have become a reality during the last decades. Implantable electronic devices have hard design constraints: 1) As small size as possible to reduce tissue damage, 2) Minimum heat generation to protect the surrounding tissue, and 3) Minimum energy dissipation as these devices are mostly operated using a small battery or wireless power transfer. The advancement and scaling of CMOS technologies has always been based on improving the performance of digital systems. With each new technology node, the threshold voltages of the available MOS transistors and the supply voltage of the process node is scaled as well. Scaling of the supply voltage reduces the headroom that is available to the transistors for operating in the region. Even though reducing the supply voltage reduces the energy dissipation, without transistors operating in the saturation region, it is very hard to realize signal processing and amplification functions in the analogue domain. To address the mentioned hard constraints of implantable electronic device design, we propose time-mode circuits for energy efficient sampling and conversion of bio-signals in advanced process technologies. The types of circuits we are proposing benefit both from voltage scaling and smaller size of advanced process nodes while being able to process digital signals with analogue accuracy, i.e., time-mode circuits represent an analogue signal by the time difference between two binary switching events. For example, when compared to standard digital CMOS circuit operation, to transfer N bits of data in parallel, the number of switchings required may change from 0 to N in standard CMOS, while it always takes timemode circuits two switching if the rising and falling edges of a pulse is used for signal representation. Based on these observations, we designed a bio-signal sampling and conversion system that consists of an analogue-to-time converter (ATC) followed by an asynchronous time-to-digital converter (A-TDC). The ATC converts the sampled bio-signal to a time-pulse with a high analogue-to-time conversion gain, and the A-TDC resolves this generated pulse to a digital value, completing the sampling and conversion process. We will present the design process and simulation results of such an implementation that operates with a supply voltage of 0.6V in a standard 0.18um process.
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With the continuous developments in science and engineering, specifically in the fields of electronics and manufacturing, implantable electronic devices have become a reality during the last decades. Implantable electronic devices have hard design constraints: 1) As small size as possible to reduce tissue damage, 2) Minimum heat generation to protect the surrounding tissue, and 3) Minimum energy dissipation as these devices are mostly operated using a small battery or wireless power transfer. The advancement and scaling of CMOS technologies has always been based on improving the performance of digital systems. With each new technology node, the threshold voltages of the available MOS transistors and the supply voltage of the process node is scaled as well. Scaling of the supply voltage reduces the headroom that is available to the transistors for operating in the region. Even though reducing the supply voltage reduces the energy dissipation, without transistors operating in the saturation region, it is very hard to realize signal processing and amplification functions in the analogue domain. To address the mentioned hard constraints of implantable electronic device design, we propose time-mode circuits for energy efficient sampling and conversion of bio-signals in advanced process technologies. The types of circuits we are proposing benefit both from voltage scaling and smaller size of advanced process nodes while being able to process digital signals with analogue accuracy, i.e., time-mode circuits represent an analogue signal by the time difference between two binary switching events. For example, when compared to standard digital CMOS circuit operation, to transfer N bits of data in parallel, the number of switchings required may change from 0 to N in standard CMOS, while it always takes timemode circuits two switching if the rising and falling edges of a pulse is used for signal representation. Based on these observations, we designed a bio-signal sampling and conversion system that consists of an analogue-to-time converter (ATC) followed by an asynchronous time-to-digital converter (A-TDC). The ATC converts the sampled bio-signal to a time-pulse with a high analogue-to-time conversion gain, and the A-TDC resolves this generated pulse to a digital value, completing the sampling and conversion process. We will present the design process and simulation results of such an implementation that operates with a supply voltage of 0.6V in a standard 0.18um process.
Conference paper
(2019)
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Omer Can Akgun, Mauro Mangia, Fabio Pareschi, Riccardo Rovatti, Gianluca Setti, Wouter A. Serdijn
This paper presents the design of an ultra-low energy, rakeness-based compressed sensing (CS) system that utilizes time-mode (TM) signal processing (TMSP). To realize TM CS operation, the presented implementation makes use of monostable multivibrator based analog-to-time converters, fixed-width pulse generators, basic digital gates and an asynchronous time-to-digital converter. The TM CS system was designed in a standard 0.18 µm IC process and operates from a supply voltage of 0.6V. The system is designed to accommodate data from 128 individual sensors and outputs 9-bit digital words with an average reconstruction SNR of 35.31 dB, a compression ratio of 3.2, with an energy dissipation per channel per measurement vector of 0.621 pJ at a rate of 2.23 k measurement vectors per second.
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This paper presents the design of an ultra-low energy, rakeness-based compressed sensing (CS) system that utilizes time-mode (TM) signal processing (TMSP). To realize TM CS operation, the presented implementation makes use of monostable multivibrator based analog-to-time converters, fixed-width pulse generators, basic digital gates and an asynchronous time-to-digital converter. The TM CS system was designed in a standard 0.18 µm IC process and operates from a supply voltage of 0.6V. The system is designed to accommodate data from 128 individual sensors and outputs 9-bit digital words with an average reconstruction SNR of 35.31 dB, a compression ratio of 3.2, with an energy dissipation per channel per measurement vector of 0.621 pJ at a rate of 2.23 k measurement vectors per second.
This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and
simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step. ...
simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step. ...
This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and
simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.
simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.