Correction to: Nature Communicationshttps://doi.org/10.1038/s41467-024-55298-4, published online 02 January 2025 In this article the following sentence was omitted from the acknowledgements section, ‘This research was funded by the following projects: Project CANDO (Controlling Network Dynamics with Optogenetics), funded by UK EPSRC (grant ref: NS/A000026/1) and the Wellcome Trust (contract ref: 102037/Z/13/Z)’. The original article has been corrected.

Miniaturization of next-generation active neural implants requires novel micro-packaging solutions that can maintain their long-term coating performance in the body. This work presents two thin-film coatings and evaluates their biostability and in vivo performance over a 7-month animal study. To evaluate the coatings on representative surfaces, two silicon microchips with different surface microtopography are used. Microchips are coated with either a ≈100 nm thick inorganic hafnium-based multilayer deposited via atomic layer deposition (ALD-ML), or a ≈6 µm thick hybrid organic–inorganic Parylene C and titanium-based ALD multilayer stack (ParC-ALD-ML). After 7 months of direct exposure to the body environment, the multilayer coatings are evaluated using optical and cross-sectional scanning electron microscopy. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) is also used to evaluate the chemical stability and barrier performance of the layers after long-term exposure to body media. Results showed the excellent biostability of the 100 nm ALD-ML coating with no ionic penetration within the layer. For the ParC-ALD-ML, concurrent surface degradation and ion ingress are detected within the top ≈70 nm of the outer Parylene C layer. The results and evaluation techniques presented here can enable future material selection, packaging, and analysis, enhancing the functional stability of future chip-embedded neural implants.

Active neural interfaces for bioelectronic medicine are envisioned to be mm-sized. Such miniaturization is at the moment hampered by the available wireless power techniques as well as the large volume the conventional hermetic packaging adds to the implant. Alternatively, conformal coatings are being explored for the protection of the implant electronics. Such approach has the potential to allow for the use of RF (radio-frequency) energy for powering, and miniaturization to the extreme of having a single IC (integrated circuit) as the whole implant (single chip implants). The longevity of conformal encapsulation can be assessed using accelerated soak tests in a dedicated apparatus in vitro, but these are usually not sufficient, as they fail to reveal additional failure modes that manifest themselves in vivo. Therefore, to investigate the performance of conformal coatings in vivo a compact, mm-sized wireless monitoring system is required. The development of such a system exhibits several challenges, mostly concerned with how to receive enough energy in such a small implant to power the monitoring sensor and transmit information regarding the integrity of the coating. In this paper we propose a system architecture for such a mm-sized wireless system, suitable for medium-to-Iong term monitoring of implants, by designing the whole system as a single monolithic IC. It is shown, by experiments, simulation or analytically that the identified challenges are possible to overcome, allowing to proceed towards the practical prototype.

Objective. Ensuring the longevity of implantable devices is critical for their clinical usefulness. This is commonly achieved by hermetically sealing the sensitive electronics in a water impermeable housing, however, this method limits miniaturisation. Alternatively, silicone encapsulation has demonstrated long-term protection of implanted thick-film electronic devices. However, much of the current conformal packaging research is focused on more rigid coatings, such as parylene, liquid crystal polymers and novel inorganic layers. Here, we consider the potential of silicone to protect implants using thin-film technology with features 33 times smaller than thick-film counterparts. Approach. Aluminium interdigitated comb structures under plasma-enhanced chemical vapour deposited passivation (SiO x , SiO x N y , SiO x N y + SiC) were encapsulated in medical grade silicones, with a total of six passivation/silicone combinations. Samples were aged in phosphate-buffered saline at 67 °C for up to 694 days under a continuous 5 V biphasic waveform. Periodic electrochemical impedance spectroscopy measurements monitored for leakage currents and degradation of the metal traces. Fourier-transform infrared spectroscopy, x-ray photoelectron spectroscopy, focused-ion-beam and scanning-electron- microscopy were employed to determine any encapsulation material changes. Main results. No silicone delamination, passivation dissolution, or metal corrosion was observed during ageing. Impedances greater than 100 GΩ were maintained between the aluminium tracks for silicone encapsulation over SiO x N y and SiC passivations. For these samples the only observed failure mode was open-circuit wire bonds. In contrast, progressive hydration of the SiO x caused its resistance to decrease by an order of magnitude. Significance. These results demonstrate silicone encapsulation offers excellent protection to thin-film conducting tracks when combined with appropriate inorganic thin films. This conclusion corresponds to previous reliability studies of silicone encapsulation in aqueous environments, but with a larger sample size. Therefore, we believe silicone encapsulation to be a realistic means of providing long-term protection for the circuits of implanted electronic medical devices.

For mm-sized implants incorporating silicon integrated circuits, ensuring lifetime operation of the chip within the corrosive environment of the body still remains a critical challenge. For the chip's packaging, various polymeric and thin ceramic coatings have been reported, demonstrating high biocompatibility and barrier properties. Yet, for the evaluation of the packaging and lifetime prediction, the conventional helium leak test method can no longer be applied due to the mm-size of such implants. Alternatively, accelerated soak studies are typically used instead. For such studies, early detection of moisture/ion ingress using an in-situ platform may result in a better prediction of lifetime functionality. In this work, we have developed such a platform on a CMOS chip. Ingress of moisture/ions would result in changes in the resistance of the interlayer dielectrics (ILD) used within the chip and can be tracked using the proposed system, which consists of a sensing array and an on-chip measurement engine. The measurement system uses a novel charge/discharge based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18 μm 6-metal CMOS process. The platform was validated through a series of dry and wet measurements. The system can measure the ILD resistance with values of up to 0.504 peta-ohms, with controllable measurement steps that can be as low as 0.8 MΩ. The system works with a supply voltage of 1.8 V, and consumes 4.78 mA. Wet measurements in saline demonstrated the sensitivity of the platform in detecting moisture/ion ingress. Such a platform could be used both in accelerated soak studies and during the implant's life-time for monitoring the integrity of the chip's packaging.

To meet the dimensional requirements for bioelectronic medicine, new packaging solutions are needed that could enable small, light-weight and flexible implants. For protecting the implantable electronics against biofluids, recently various atomic layer deposited (ALD) coatings have been proposed with high barrier properties. Before implantation, however, the protective coating should be evaluated for any defects which could otherwise lead to leakage and device failure. In these cases, the conventional helium leak test method can no longer be used due to the millimeter size of the implant. Therefore, an in-situ sensing platform is needed that could evaluate the coating and justify the implantation of the final device. In this work, we explore the possibility of using the CMOS bulk for such a platform. Towards this aim, as a proof of concept, test chips were made in a standard 6-metal 0.18 μm CMOS process and for the connection to the bulk, a p+ diffusion was used. A group of samples was then coated with an ALD multilayer. For coating evaluation, off-chip DC current leakage and impedance measurements were carried out in saline between the CMOS bulk and a platinum reference electrode. Results were compared between non-coated and coated chips that clearly demonstrated the potential of using the bulk as a sensing platform for coating evaluations. This novel approach could pave the way towards an all integrated in-situ hermeticity test, currently missing in mm-size implants.