Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

Comparative analysis of soft and hard on-chip interconnects for FPGAs

Customizing and Hardwiring On-chip Interconnects in FPGAs

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

Design trade-offs in customized on-chip crossbar schedulers

Partilially reconfigurable point-to-point FPGA interconnects

Performance analyses of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs

FPGA Implementation of Parallel Histogram Computation

Hardwired networks on chip in FPGAs to unify functional and configuration interconnects

Partially reconfigurable point-to-point interconnects in virtex-II pro FPGAs

Systematic customization of on-chip crossbar intervconnects

Customizing reconfigurable on-chip crossbar scheduler

Parallel merge sort on a binary tree on-chip network

Implementation of a dual analog decoder