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JY Hur
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Authored
14 records found
Parallel merge sort on a binary tree on-chip network
Conference paper -
J.S.S.M. Wong
,
S Vassiliadis
,
JY Hur
Customizing and Hardwiring On-chip Interconnects in FPGAs
Doctoral thesis -
JY Hur
Performance analyses of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs
Conference paper -
JY Hur
,
K.G.W. Goossens
,
L. Mhamdi
Design trade-offs in customized on-chip crossbar schedulers
Journal article -
JY Hur
,
J.S.S.M. Wong
,
T.P. Stefanov
FPGA Implementation of Parallel Histogram Computation
Conference paper -
A. Shahbahrami
,
JY Hur
,
B.H.H. Juurlink
,
J.S.S.M. Wong
Systematic customization of on-chip crossbar intervconnects
Conference paper -
JY Hur
,
T.P. Stefanov
,
J.S.S.M. Wong
,
S Vassiliadis
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices
Conference paper -
TM Thomas
,
JY Hur
,
K.L.M. Bertels
,
G. Gaydadjiev
Customizing reconfigurable on-chip crossbar scheduler
Conference paper -
JY Hur
,
T.P. Stefanov
,
J.S.S.M. Wong
,
S Vassiliadis
Partially reconfigurable point-to-point interconnects in virtex-II pro FPGAs
Conference paper -
JY Hur
,
J.S.S.M. Wong
,
S Vassiliadis
Hardwired networks on chip in FPGAs to unify functional and configuration interconnects
Conference paper -
K.G.W. Goossens
,
M Bennebroek
,
JY Hur
,
M.A. Wahlah
Implementation of a dual analog decoder
Conference paper -
JY Hur
,
J.S.S.M. Wong
,
S.D. Cotofana
Partilially reconfigurable point-to-point FPGA interconnects
Journal article -
JY Hur
,
J.S.S.M. Wong
,
S Vassiliadis
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
Journal article -
JY Hur
,
T.P. Stefanov
,
J.S.S.M. Wong
,
K.G.W. Goossens
Comparative analysis of soft and hard on-chip interconnects for FPGAs
Journal article -
JY Hur
,
K.G.W. Goossens
,
L. Mhamdi
,
M.A. Wahlah