12 records found
1
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
IP-XACT Extensions for Reconfigurable Computing
Optimal loop unrolling and shifting for reconfigurable architectures
Flexible pipelining design for recursive variable expansion
Efficient hardware generation for dynamic programming problems
Loop optimizations for reconfigurable architectures
System-level dynamic exploration and mapping for dynamic reconfigurable system
Design trade-offs in customized on-chip crossbar schedulers
System-level design space exploration of dynamic reconfigurable architectures
Loop unrolling and shifting for reconfigurable architectures
Systematic customization of on-chip crossbar intervconnects
Customizing reconfigurable on-chip crossbar scheduler
