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Luca Benini

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Design and Experimental Characterization of a Fault-Tolerant 28-nm RISC-V-Based SoC

Journal article (2025) - Michael Rogenmoser, Philip Wiese, Bruno Endres Forlin, Frank K. Gurkaynak, Paolo Rech, Alessandra Menicucci, Marco Ottavi, Luca Benini
RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires characterization under controlled radiation doses to accurately quantify the fault tolerance of the fabricated designs. This work analyzes the Trikarenos design, an SoC implemented in TSMC 28 nm, for single event upset (SEU) vulnerability under atmospheric neutron and 200-MeV proton radiation, comparing these results to simulation-based fault injection. All faults in error correction codes (ECCs) protected memory are corrected by a scrubber, showing an estimated cross section per bit of up to 1.09 × 10-14 cm2bit−1. Furthermore, the triple-core lockstep (TCLS) mechanism implemented in Trikarenos is validated and is shown to correct errors affecting a cross section up to 3.23 × 10-11 cm2, with the remaining uncorrectable vulnerability below 5.36 × 10-12 cm2. When augmenting the experimental analysis of fabricated chips with gate-level fault injection in simulation, 99.10% of injections into the SoC produced correct results, while 100% of injections in the TCLS-protected cores were handled correctly. With 12.28% of all injected faults leading to a TCLS recovery, this indicates an approximate effective flip-flop (FF) cross section of up to 1.28 ×10-14 cm2/FF. ...
Conference paper (2019) - Said Hamdioui, Hoang Anh Du Nguyen, G. Karunaratne, Abbas Rahimi, Luca Benini, Mottaqiallah Taouil, Abu Sebastian, Manuel Le Gallo, Sandeep Pande, Siebren Schaafsma, Francky Catthoor, Shidhartha Das, Fernando G. Redondo
Today's computing architectures and device technologies are unable to meet the increasingly stringent demands on energy and performance posed by emerging applications. Therefore, alternative computing architectures are being explored that leverage novel post-CMOS device technologies. One of these is a Computation-in-Memory architecture based on memristive devices. This paper describes the concept of such an architecture and shows different applications that could significantly benefit from it. For each application, the algorithm, the architecture, the primitive operations, and the potential benefits are presented. The applications cover the domains of data analytics, signal processing, and machine learning. ...