This thesis discusses the digital signal processing involved in building a Vector Network Analyser for qubit readout. Existing VNAs are aggregated and used to construct a programme of requirements for this application. An architecture is constructed and explained, and the stages IQ decomposition and data reduction are analysed mathematically. The Discrete Fourier Transform is used to extract DC signals for this application and its properties are compared to different filters. Common digital logic functions such as AXI, Direct Digital Synthesis, and Direct Memory Access are explained, as well as the implementations of custom blocks for this application such as accumulators and a sequencer. These IP blocks are demonstrated individually and integrated to be implemented on a Red Pitaya STEMLab 125-14 board containing the Zynq 7010 SoC. The implementation is tested using simulated input signals and the resulting measurements are analysed. The implementation is found to have good absolute accuracy of within 2% of expected absolute amplitude, 1% of the expected relative amplitude and 8 mrad of expected relative phase. Modulation of the input signals is tested to work as expected and no major cross-modulation is found. Future improvements are identified and the limitations of the used data reduction are discussed in relation to a Vector Signal Analyser mode.