Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts; a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.@en

Many march tests have already been designed to cover faults of different fault models. The complexity of these tests arises when linked faults are taken into consideration. This paper gives an overview of the most important and commonly used fault models, including the industry's popular disturb fault model. The fault coverage of march tests is analysed in a novel way, i.e., in terms of their detection capabilities for: simple faults, and linked faults; whereby the infinite class of linked faults has been reduced to a set of realistic linked faults. Thereafter, the paper presents a methodology to design tests for realistic linked faults, resulting in the new tests March LR, March LRD and March LRDD. These new tests will be shown to be more efficient and to offer a higher fault coverage than comparable existing tests.@en

A test is presented for detecting simple memory faults as well as linked memory faults. It assumes the multiple linked faults as a set of involved simple faults and guarantees their detection by detecting the simple faults belonging to the set.@en

The complexity of memory tests arises when linked faults are taken into consideration. Usually only the class of linked faults in the memory cell array have been taken into consideration, while the class of linked faults involving address decoder faults has been ignored. This paper gives an overview of the most important and commonly used fault models, including the disturb fault model. It derives a set of conditions march tests have to satisfy in order to detect address decoder faults (AFs) when they are not linked; these conditions are shown to be dependent on the memory technology (SRAM and DRAM). Next, a set of conditions for march tests are derived to detect linked AFs (linked with other AFs or linked with faults in the memory cell array). The paper concludes with the analysis of a set of well-known march tests for the fault coverage of unlinked and linked AFs. Many of the widely used tests are shown not to be able to detect all (linked) AFs.@en

The problem of designing memory tests ts to establish a relevant set of fault models only consisting of those faults which are shown to be possible to occur in practice. Thereafter, it is a challenge to the test designer to design an optimum test covering the faults of the established fault models. A new fault model, the disturb fault model, is introduced. The notition of linked faults is established and it is shown that march tests can only detect a subset of all linked faults. Thereafter, the universe of linked faults is reduced to the set of realistic linked faults. Last, the effectiveness of the realistic linked fault model is shown via new tests with a higher fault coverage and a shorter test lenght.@en