Due to their large number of high-precision, defect-prone manufacturing steps, integrated circuits (ICs) are susceptible to manufacturing defects and hence need to undergo electrical tests to weed out the defective parts and guarantee sufficient outgoing product quality to the customer. A key step in test development for digital logic ICs is automatic test pattern generation (ATPG). Cell-aware test (CAT) is a next-generation test pattern generation approach; its novel feature is that it explicitly addresses cell-internal defects (as opposed to relying on serendipitous coverage by traditional ATPG). CAT consists of two stages - cell-aware library characterization (CA-LC) and cell-aware ATPG. Library characterization uses parasitics-extracted transistor-level netlists to model open and short defects candidates, which are then simulated with an exhaustive set of cell-level test patterns. The results are encoded in the form of defect detection matrices (DDMs). Cell-aware ATPG uses this information to determine a set of test patterns such that, as many as possible cell-internal defects in the circuit are covered. As an industrial standard-cell library contains hundreds of cells, library characterization is a time consuming task. The target defect set must be realistic and complete, but not unnecessarily large. The objective of this thesis is to improve the library characterization stage of the Cadence CAT flow by effectively and efficiently modelling realistic defects, while trying to minimize the time required for characterization. To achieve this, several improvements to the existing flow are proposed. (1) defining a set of customized settings for the parasitics extraction tool for generating transistor-level netlists, which are well-suited for cell-aware defect modelling (2) elimination of potential defects, which were superfluous elements being inserted into the netlist (3) using super-hard defect resistance values for modelling opens and shorts (4) reduction in simulation time by modifying the software flow and, (5) inserting a single short defect between two net pairs to reduce the size of the target defect set. For the 45nm generic library (GPDK045) from Cadence, these modifications resulted in an improvement in test quality by uncovering as many as 1114 false detections and a reduction of 6% in the characterization time. The number of short defects to be simulated reduced by 97.7%. This work was carried out as a part of a joint project on cell-aware test between Cadence (supplier of electronic design automation software), IMEC (research organization), and Eindhoven University of Technology.