9 records found
1
A DfT architecture and tool flow for 3-D SICs with test data compression, embedded cores, and multiple towers
Yield Improvement for 3D wafer-to-wafer stacked ICs using wafer matching
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface
Quality versus cost analysis for 3D Stacked ICs
Interconnect test for 3D stacked memory-on-logic
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Using 3D-COSTAR for 2.5D test cost optimization
Impact of mid-bond testing in 3D stacked ICs
3D-COSTAR: a cost model for 3D stacked ICs
