Automotive semiconductor industry has the most critical requirement of quality and hence, pursuits for zero defects. However, due to aggressive scaling, this pursuit has been challenged by the test escapes due to latent gate oxide shorts, despite of being subjected to voltage stress testing using Pseudo Stuck-At test patterns to screen out potential latent gate oxide shorts. This demonstrates an uncertainty that has been prevailing in the semiconductor testing industry, ‘are we stressing enough ?’. Also, the complexity of digital circuits combined with the test time requirements makes 100% fault coverage an unrealistic target. Therefore, to ensure a high screening effect, the most primitive need is to know how many transistors are really experiencing the stress and how to preclude stress test escapes. This thesis presents a novel solution to optimize the voltage stress methodology in digital ICs which can be subdivided into three methods. First method, ‘Critical Thickness Model’ answers the question ‘are we stressing enough?’ by finding out the minimum stress time for n and p type MOSFETs having their gate oxide thickness in sub-3nm range. Second method, ‘Stress Coverage Quantification Algorithm’ shows the real defect coverage by finding out the percentage of transistors being stressed by each pattern and by whole pattern set. And, third method, ‘Coverage Maximization Algorithm’ minimizes the chances of customer returns due to gate oxides shorts by minimizing the test escapes. The optimality of stress is considered to be based on criticality of the application and the considered case is of automotive grade ICs. Critical Thickness Model is elicited from Thinning Model and Direct Tunneling Model and deals with elimination of early product failures. It is shown how Critical Thickness Model calculates minimum stress time for latent gate oxide shorts and hence minimizes yield loss. Stress Coverage Quantification Algorithm (SCQA) has been applied to real dataset of a test chip for Pseudo Stuck-At test pattern set and the simulation results when compared with ATPG calculated coverage for the same test pattern set showed a coverage loss of 5% at transistor level. Coverage Maximization Algorithm (CMA) is based on Greedy algorithm and was also applied to the real dataset of the same test chip and the simulation results yielded an approximately 10% of reduction in the occurrence of stress test escapes. This thesis also discusses over how, effectiveness of screening can further be enhanced by having stress aware pattern generation and presents advantages and drawbacks of under-stressing and over-stressing.