Automotive semiconductor industry has the most critical requirement of quality and hence, pursuits for zero defects. However, due to aggressive scaling, this pursuit has been challenged by the test escapes due to latent gate oxide shorts, despite of being subjected to voltage stress testing using Pseudo Stuck-At test patterns to screen out potential latent gate oxide shorts. This demonstrates an uncertainty that has been prevailing in the semiconductor testing industry, ‘are we stressing enough ?’. Also, the complexity of digital circuits combined with the test time requirements makes 100% fault coverage an unrealistic target. Therefore, to ensure a high screening effect, the most primitive need is to know how many transistors are really experiencing the stress and how to preclude stress test escapes. This thesis presents a novel solution to optimize the voltage stress methodology in digital ICs which can be subdivided into three methods. First method, ‘Critical Thickness Model’ answers the question ‘are we stressing enough?’ by finding out the minimum stress time for n and p type MOSFETs having their gate oxide thickness in sub-3nm range. Second method, ‘Stress Coverage Quantification Algorithm’ shows the real defect coverage by finding out the percentage of transistors being stressed by each pattern and by whole pattern set. And, third method, ‘Coverage Maximization Algorithm’ minimizes the chances of customer returns due to gate oxides shorts by minimizing the test escapes. The optimality of stress is considered to be based on criticality of the application and the considered case is of automotive grade ICs. Critical Thickness Model is elicited from Thinning Model and Direct Tunneling Model and deals with elimination of early product failures. It is shown how Critical Thickness Model calculates minimum stress time for latent gate oxide shorts and hence minimizes yield loss. Stress Coverage Quantification Algorithm (SCQA) has been applied to real dataset of a test chip for Pseudo Stuck-At test pattern set and the simulation results when compared with ATPG calculated coverage for the same test pattern set showed a coverage loss of 5% at transistor level. Coverage Maximization Algorithm (CMA) is based on Greedy algorithm and was also applied to the real dataset of the same test chip and the simulation results yielded an approximately 10% of reduction in the occurrence of stress test escapes. This thesis also discusses over how, effectiveness of screening can further be enhanced by having stress aware pattern generation and presents advantages and drawbacks of under-stressing and over-stressing.

Epilepsy is a medical condition which is caused by excessive or synchronous neuronal activity of the brain cells. These activities can lead to attacks where the patient can lose conciseness or experiences random muscle cramps at seemingly any point in time. Using implantable on body sensors these seizure attacks could be detected and even prevented. These sensors would form a Medical Body Area Network (MBAN) which interconnects all of the sensors. This project looks at a proof of concept implementation of such an MBAN and focuses on a secure connection between an implant and a gateway device, which is a mobile phone. The implant and mobile phone will communicate with each other using Bluetooth Low Energy (BLE). This form of communication does not provide a secure pairing method for devices that lack in- and output capabilities, such as an implant. To set up a secure connection the data will be encrypted with an encryption key, which has to be shared between the implant and mobile phone. In order to do this in a secure way, an Out Of Band (OOB) channel will be used to pair the two devices. This thesis looks at three different OOB channels, Near Field Communication (NFC), ultrasound and galvanic coupling and compares them in therms of security, health safety, data rate, power consumption and feasibility.

With recent breakthroughs in AI and deep learning, applying these techniques to on-board computers for space applications has grown in interest to engineers on space applications. The space field brings its own challenges, such as reliability and power restrictions. The proposed solution in this work concerns a neuromorphic accelerator for a spiking neural network (SNN) designed using memristive devices (RRAM), dubbed the Newtype Learning Computer. To this end, this work presents the following contributions: A design for a behavioral VHDL implementation of a target SNN boasting software-level accuracy, specifically built for edge AI in space. We also present a characterized ASIC design of one layer of this SNN, analyzed using RTL design tools. An analysis of this same layer designed using Memristive Crossbar Arrays is also provided, and we present a comparison of both. When simulating 4096 neurons, the RRAM-based design shows 174x smaller area, power dissipation reduction of 27x energy reduction by 4 orders of magnitude and over 80x faster by latency compared to the CMOS-based design. This thesis presents a confident first step towards the use of RRAM-based neuromorphic accelerators for spiking neural networks in space-based applications.