Two P-Based depth of SiC VDMOSFETs (group A and B) are designed and manufactured by enhanced P-Based implantation. The group A with lower P-based depth has a better static properties, while group B has a higher high frequency switching performance. Further, the avalanche reliability and failure mechanism for two groups are investigated by UIS experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. Significantly, high P-Based depth exhibits higher UIS reliability due to smaller Rb and more difficult to active parasitic BJT.

The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L JFET=1.4μ m has the best HF-FOM (R on × Cgd) and HF-FOM (R on × Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.