Characteristics and avalanche investigation of SiC VDMOSFETs with enhanced P-Based implantation
Hou-Cai Luo (Chongqing University)
Jingping Zhang (Chongqing University)
Huan Wu (Chongqing University)
Bo Feng Zheng (Chongqing University)
Xiao Wang (Chongqing University)
Kai Zheng (Chongqing University)
Guo Qi Zhang (TU Delft - Electronic Components, Technology and Materials)
X.P. Chen (Chongqing University)
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Abstract
Two P-Based depth of SiC VDMOSFETs (group A and B) are designed and manufactured by enhanced P-Based implantation. The group A with lower P-based depth has a better static properties, while group B has a higher high frequency switching performance. Further, the avalanche reliability and failure mechanism for two groups are investigated by UIS experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. Significantly, high P-Based depth exhibits higher UIS reliability due to smaller Rb and more difficult to active parasitic BJT.