The neuromodulation modality based on the focused ultrasonic stimulation (FUS) has gained its interests for being non-invasive while having unprecedented high spatial resolution and deep penetration. The commercially available image-guided FUS device for neuromodulation setups are normally bulky, by employing an 1-D array transducer element to produce the FUS and a separate ultrasonic scanning device for B-Mode imaging purpose. Aiming to design a wearable neural stimulating device for human's vagus nerve, a miniature device with 2-D array transducers is proposed to replace the conventional setup as it can statically generate FUS. The device is capable of locating the vagus nerve and non-invasively stimulating the nerve by integrating the imaging system and the neural modulation system together. In typical neuroFUS applications, an ultrasound image is obtained prior to neuromodulation, to obtain the precise coordinates of the nerve. This project presents a front-end CMOS circuit for the 2-D array ultrasound-based system for imaging the vagus nerve, as a part of the full system for the neuromodulation capabilities. The imaging signal chain enables the local digitization, allowing a robust digital beamforming and readout signal.
The front-end CMOS circuit mainly contains three functions: the low-noise amplifier (LNA), time-gain-compensation (TGC) function block and the analog-to-digital converter (ADC). The front-end received chain employs the power- and area-efficient design consideration, interfacing the 12 MHz piezoelectric signal from the PMN-PT transducer element. The mixed signal system is implemented in 0.18 micrometer TSMC CMOS technology and operating under the 1.8 V voltage for both analog and digital supply. The analog front end (AFE) has the variable voltage gains up to 62 dB to interface the 1 V full scale range of the ADC. For ultra low power and chip area considerations, the ADC topology is a 6-bit single-ended common-voltage based successive-approximation (SAR) ADC with the typical sample rate 50 MS/s. The SAR ADC consumes 415.8 microW and achieves dynamic performances of 37 dB SNDR and 49.4 dB SFDR. The total power consumption of the signal chain is 1.3 mW and the layout chip area consumes 150 micrometer square.