As technologies in embedded systems are rapidly advancing, possibilities are opening up in many research fields. Neuroscience is one of those fields. Research on the brain is crucial for medial applications such as seizure prevention, understanding neurological disorders like Parkinson's disease and developing Brain Machine Interfaces for prosthetics. In order to make accurate neural recordings, invasive techniques like Intracortical electrophysiology (IC-Ephys) are often required. Using tiny probes, neural signals are measured directly from the brain tissue. These experiments are almost always performed on animals because of the health risks that they pose.

The Neuroscience department at the Erasmus Medical Center (EMC) has been conducting these sorts of experiments on mice using either wired or battery-based neural recording devices (Neurologgers). These devices simply make neural recordings without processing the data in any other way. To get the most realistic neural response in the brain, the mouse should be free to move and not be limited by the recording device. Ideally, signal processing and spike detection is done immediately on the device, so that it outputs useful data instead of raw data.

For these reasons our group was given the task by the Neuroscience department to make a battery-based neural-logging device containing an FPGA for real-time signal processing and spike detection. In this thesis, the design process, implementation and validation of the hardware of this so called Neurologger is discussed.

We were able to make a compact design that weighs 4.139 g without battery. It has an FPGA which performs real-time signal processing and spike detection. Two neural probes can be attached to perform neural recordings in multiple parts of the brain. Finally, 64 channels can be recorded simultaneously at a sampling rate of 20 kHz.

This thesis also contains a proposal for an even smaller Neurologger design. Making specific design choices, more channels can be recorded with a device that has a significantly smaller surface area than the current design.