Capacitive micromachined ultrasonic transducer (CMUT) technology has been considered as a promising alternative for the conventional piezo electric-based technology in ultrasound imaging systems. Its potential advantages include better image quality, higher operational frequency, and ease of fabrication and
integration with CMOS read-out circuitry. However, CMUTs usually need high-voltage DC bias in order to transmit and receive acoustic waves. This work presents the design of a DC-DC converter to bias a CMUT for ultrasound imaging systems. Two different cases have been investigated: biasing at 63 V from an input of 5 V using a fully-integrated converter realized in a 180nm BCD technology that can handle up to 65V; and biasing at 120 V by employing minimal off-chip components. The proposed work explores the transient properties of a conventional on-chip switched capacitor DC-DC converter: the Dickson charge pump. A MATLAB model of the Dickson charge pump is developed to understand the relation between dynamic efficiency and the charge pump capacitor. Prior research works suggest that the dynamic efficiency of the Dickson charge pump is limited for a particular number of stages. However, the results obtained from the MATLAB model suggests that the dynamic efficiency can be improved by making the charge pump capacitor smaller. Various circuit simulations have been done to understand the results obtained from the MATLAB model. When the charge pump capacitor becomes very small, the parasitics start dominating and affect the overall efficiency of the Dickson charge pump. An optimization strategy is discussed to find the optimum number of stages and charge pump capacitor value to maximize the dynamic efficiency and minimize the circuit area. Based on the results obtained from this study, a DC-DC converter is designed to bias the CMUT at 63V, which consumes an estimated circuit area of 0.6586mm2 and has a simulated efficiency of 0.752.
In addition, a new design idea that incorporates two DC-DC converters to bias the CMUT beyond the process voltage limitations is also discussed in this thesis. This hybrid converter involves the optimized DC DC converter designed earlier to generate 63V from an input of 5V, a control unit circuit, and some off-chip
components. The hybrid converter designed consumes an estimated circuit area of 0.842mm2 and has a simulated efficiency of 0.577