14 records found
1
An improved RNS reverse converter for the {2 2n+1-1, 2n, 2n-1} moduli set
Residue-to-binary converters for the moduli set {2 2n+1, 2 2n, 2n-1}
Cost-efficient SHA hardware accelerators
BRAM-LUT tradeoff on a polymorphic DES design
Merged computation for whirlpool hashing
On-the-fly attestation of reconfigurable hardware
Vectorized AES core for high-throughput secure environments
Secure computing on reconfigurable systems
Dynamic FPGA reconfigurations with run-time region delimitation
Reconfigurable memory based AES co-processor
Reconfigurable cryptographic processor
HLL-to-HDL generation: results and challenges
Improving SHA-2 hardware implementations
Rescheduling for optimized SHA-1 calculation
