In this paper, we analyze the problem of supporting conflict-free access for multiple stride families in parallel memory schemes targeted for SIMD processing systems. We propose a Single-Affiliation Multiple-Stride (SAMS) scheme to support both unit-stride and strided conflict-free vector memory accesses. We compare our scheme against other previously proposed techniques using buffers and inter-vector out-of-order access. The main advantage of our proposal is that the atomic parallel access is supported without limiting the vector lengths. This provides better support when short vectors are considered. Our scheme also has the merit of better memory module utilization compared to the solutions with additional modules. Synthesis results for reconfigurable Virtex2-Pro FPGA technology indicate that the address translation of the SAMS scheme has efficient hardware implementation, which has a logic delay of less than 3 ns and trivial hardware resource utilization.

This article investigates microcode generation, finalization and loading in MOLEN ρμ processors. In addition, general solutions for these issues are presented and implementation for Xilinx Virtex-II Pro platform FPGA is introduced.