Loading ρμ-code

Design considerations

Book chapter (2004)

Authors

G.K. Kuzmanov Computer Engineering - EEMCS
G. Gaydadjiev Computer Engineering - EEMCS
S Vassiliadis Computer Engineering - EEMCS
Research Group
Computer Engineering (EEMCS) (TU Delft)
Implementation Loading microcode MOLEN Reconfigurable architectures
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Published Date

2004

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

This article investigates microcode generation, finalization and loading in MOLEN ρμ processors. In addition, general solutions for these issues are presented and implementation for Xilinx Virtex-II Pro platform FPGA is introduced.