This thesis addresses the development of a supporting electronics platform for a CMOS Pixelated Capacitive Sensor (PCS) array intended for high-sensitivity applications. The work focuses on enabling accurate extraction of capacitance changes at the sensor interface and translating them into signals suitable for digital processing. The design process emphasizes functional integration and signal integrity.

A custom analog front-end was developed, featuring a transimpedance amplifier (TIA) optimized for low input-referred noise and sufficient bandwidth to preserve pixel-level signal integrity. The complete analog signal path supports capacitive measurements with attofarad-level resolution and readout frequencies ranging from 1 to 100 MHz.

The main PCB integrates the readout circuitry with a central microcontroller (MCXN947), DAC-controlled programmable power supplies, and a variety of user interface connectors, all within a compact six-layer mixed-signal stackup. Particular attention was given to minimizing electromagnetic interference (EMI) and power supply noise through careful grounding, power segmentation, and layout strategies. Although the PCB theoretically satisfies most mandatory and trade-off requirements, including spatial and interface constraints, final verification of the noise performance remains pending due to fabrication lead times.