Mixed signal pcb design and Analog Readout Circuitry for a Pixelated Capacitive Sensor E nose array

Bachelor Thesis (2025)
Author(s)

P. Olyslaegers (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Y. Machtane (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Contributor(s)

Frans Widdershoven – Mentor (TU Delft - Bio-Electronics)

Tao Shen – Mentor (TU Delft - Bio-Electronics)

C. Verhoeven – Graduation committee member (TU Delft - Electronics)

Faculty
Electrical Engineering, Mathematics and Computer Science
More Info
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Publication Year
2025
Language
English
Graduation Date
26-06-2025
Awarding Institution
Delft University of Technology
Project
['EE3L11 Bachelor graduation project Electrical Engineering']
Programme
['Electrical Engineering']
Faculty
Electrical Engineering, Mathematics and Computer Science
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Abstract

This thesis addresses the development of a supporting electronics platform for a CMOS Pixelated Capacitive Sensor (PCS) array intended for high-sensitivity applications. The work focuses on enabling accurate extraction of capacitance changes at the sensor interface and translating them into signals suitable for digital processing. The design process emphasizes functional integration and signal integrity.

A custom analog front-end was developed, featuring a transimpedance amplifier (TIA) optimized for low input-referred noise and sufficient bandwidth to preserve pixel-level signal integrity. The complete analog signal path supports capacitive measurements with attofarad-level resolution and readout frequencies ranging from 1 to 100 MHz.

The main PCB integrates the readout circuitry with a central microcontroller (MCXN947), DAC-controlled programmable power supplies, and a variety of user interface connectors, all within a compact six-layer mixed-signal stackup. Particular attention was given to minimizing electromagnetic interference (EMI) and power supply noise through careful grounding, power segmentation, and layout strategies. Although the PCB theoretically satisfies most mandatory and trade-off requirements, including spatial and interface constraints, final verification of the noise performance remains pending due to fabrication lead times.

Files

Thesis.pdf
(pdf | 3 Mb)
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