Debugging modern HDLs such as Chisel (Constructing Hardware In a Scala Embedded Language) remains challenging due to the lack of debugging tools operating on the source-language level. Furthermore, due to a lack of tooling, engineers often resort to manual waveform debugging, undermining productivity gains promised by such a language.

This thesis presents ChiselTrace, an open-source tool for Chisel that is capable of automatic signal dependency tracing at the Chisel source level, allowing faults to be more easily traced back to their root cause. The contributions of this work include the following. Modifications are made to the Chisel library to extract program dependence graphs and control flow graphs, and add instrumentation probes to the circuit, enabling post-simulation analysis. Furthermore, a library capable of dynamic program slicing and program dependence graph generation is introduced that is based on reconstruction from intermediate representation-level analysis. Finally, a front-end dependency graph viewer is presented, along with a method to automatically start a ChiselTrace session from failed ChiselSim unit tests.

The debugging capabilities of ChiselTrace are presented using a variety of test cases, including a real-world example, where an injected fault in the ChiselWatt processor is traced back to the source.

The creation of effective computational models that function within the power limitations of edge de- vices is an important research problem in the field of Artificial Intelligence (AI). While cutting-edge deep learning algorithms show promising results, they frequently need computing resources that are many orders of magnitude more than the available power and memory budgets for these devices. During the thesis, two unique learning algorithms (backpropagation and forward-forward) were developed and compared using the Teensy 4.1, a low-cost microcontroller board. This work seeks to bridge the gap between the necessary computing efficiency and the hardware’s restricted resources.

By creating and analyzing these algorithms, with the Fashion MNIST dataset as a validation set, this thesis creates a baseline for AI efficiency on microcontrollers, with performance targets set at a mini- mum of 80% test accuracy. The microcontroller software, implemented in C++, is limited to using less than 512 kB RAM for all online training methods. In addition, the potential of transfer learning was also explored.

Key performance parameters, including memory utilization, training and inference times, and accu- racy, were analyzed in a comparative study of the backpropagation and forward-forward algorithms. For each learning algorithm, several configurations were explored (such as topologies, and optimizers) to determine the most effective and efficient way for AI implementation on low-cost hardware. The key conclusions of this study reveal that backpropagation demonstrates superior performance in terms of both accuracy and computational efficiency. However, it requires more memory for storing variables, which may be a constraint in on-edge environments. Conversely, the forward-forward algorithm, while achieving lower accuracy, is more memory-efficient, making it a potential choice for less complex tasks or systems with severe RAM limitations.

The application of transfer learning showed potential to accelerate the learning process and to improve the final accuracy, hinting at an effective strategy for deploying advanced AI models on resource-limited edge devices.